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1. general description the lpc84x are an arm cortex-m0+ based, lo w-cost 32-bit mcu family operating at cpu frequencies of up to 30 mhz. the lpc84x support up to 64 kb of flash memory and 16 kb of sram. the peripheral complement of the lpc84x includes a crc engine, four i 2 c-bus interfaces, up to five usarts, up to two spi interfaces, capacitive touch interface, one multi-rate timer, self-wake-up timer, sctimer/pwm, one general purpose 32-bit counter/timer, a dma, one 12-bit adc, two 10-bit dacs, one analog comparator, function-configurable i/o ports through a s witch matrix, an input pattern match engine, and up to 54 general-purpose i/o pins. for additional documentation related to the lpc84x parts, see section 18 . 2. features and benefits ? system: ? arm cortex-m0+ processor (revision r0p1), running at frequencies of up to 30 mhz with single-cycle multiplier and fast single-cycle i/o port. ? arm cortex-m0+ built-in nested vect ored interrupt controller (nvic). ? system tick timer. ? ahb multilayer matrix. ? serial wire debug (swd) with four break points and two watch points. jtag boundary scan (bsdl) supported. ? micro trace buffer (mtb). ? memory: ? up to 64 kb on-chip flash programming memory with 64 byte page write and erase. ? fast initialization memory (faim) allowin g the user to configure chip behavior on power-up. ? code read protection (crp) ? up to 16 kb sram consisting of two 8 kb contiguous sram banks. one 8 kb of sram can be used for mtb. ? bit-band addressing supported to permit atomic operations to modify a single bit. ? rom api support: ? boot loader. ? supports flash in-application programming (iap). lpc84x 32-bit arm ? cortex ? -m0+ microcontroller; up to 64 kb flash and 16 kb sram; faim memo ry; 12-bit adc; 10-bit dacs; comparator; capaciti ve touch interface rev. 1.7 ? 27 february 2018 product data sheet
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 2 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller ? supports in-system programming (isp) through usart, spi, and i 2 c. ? faim api. ? fro api. ? on-chip rom apis for integer divide. ? digital peripherals: ? high-speed gpio interface connected to the arm cortex-m0+ i/o bus with up to 54 general-purpose i/o (gpio) pins with conf igurable pull-up/pu ll-down resistors, programmable open-drain mode, input inverter, and digital filter. gpio direction control supports independent set/clear/toggle of individual bits. ? high-current source output driver (20 ma) on four pins. ? high-current sink driver (20 ma) on two true open-drain pins. ? gpio interrupt generation cap ability with boolean pattern-m atching feature on eight gpio inputs. ? switch matrix for flexible config uration of each i/o pin function. ? crc engine. ? dma with 25 channels and 13 trigger inputs. ? capacitive touch interface. ? timers: ? one sctimer/pwm with five input and sev en output functions (including capture and match) for timing and pwm applications . inputs and outputs can be routed to or from external pins and internally to or from selected perip herals. internally, the sctimer/pwm supports 8 match/capt ures, 8 events, and 8 states. ? one 32-bit general purpose counter/timer, with four match outputs and three capture inputs. supports pwm mode, external count, and dma. ? four channel multi-rate timer (mrt) for repetitive interrupt generation at up to four programmable, fixed rates. ? self-wake-up timer (wkt) clocked from ei ther free running oscillator (fro), a low-power, low-frequency internal oscillato r, or an external clock input in the always-on power domain. ? windowed watchdog timer (wwdt). ? analog peripherals: ? one 12-bit adc with up to 12 input channel s with multiple inte rnal and external trigger inputs and with sample rates of up to 1.2 msamples/s. the adc supports two independent conversion sequences. ? comparator with five input pins and external or internal reference voltage. ? two 10-bit dacs. ? serial peripherals: ? five usart interfaces with pin functions assigned through the switch matrix and two fractional baud rate generators. ? two spi controllers with pin functions assigned through the switch matrix. ? four i 2 c-bus interfaces. one i 2 c supports fast-mode plus with 1 mbit/s data rates on two true open-drain pins and listen mode. three i 2 cs support data rates up to 400 kbit/s on standard digital pins. ? clock generation:
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 3 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller ? free running oscillator (fro). this oscillator provides a selectable 18 mhz, 24 mhz, and 30 mhz outputs that can be used as a system clock. also, these outputs can be divided down to 1.125 mhz, 1.5 mh z, 1.875 mhz, 9 mhz, 12 mhz, and 15 mhz for system clock. the fro is trimmed to ? 1 % accuracy over the entire voltage and temperature range of 0 c to 70 c. ? low power boot at 1.5 mhz using faim memory. ? external clock input for clock frequencies of up to 25 mhz. ? crystal oscillator with an operat ing range of 1 mhz to 25 mhz. ? low power oscillator can be used as a clock source to the watchdog timer. ? programmable watchdog osc illator with a frequency range of 9.4 khz to 2.3 mhz. ? pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from the system oscilla tor, the external clock input, or the internal fro. ? clock output function with divider that can reflect all internal clock sources. ? power control: ? reduced power modes: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. ? wake-up from deep-sleep and power-down modes on activity on usart, spi, and i2c peripherals. ? timer-controlled self wake-up from deep power-down mode. ? power-on reset (por). ? brownout detect (bod). ? unique device serial number for identification. ? single power supply (1.8 v to 3.6 v). ? operating temperature range -40 c to +105 c. ? available in lqfp64, lqfp48, hvqfn48, and hvqfn33 packages. 3. applications ? sensor gateways ? simple motor control ? industrial ? portables and wearables ? gaming controllers ? lighting ? 8/16-bit applications ? motor control ? consumer ? fire and security applications ? climate control
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 4 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 4. ordering information 4.1 ordering options table 1. ordering information type number package name description version lpc845m301jbd64 lqfp64 plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc845m301jbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 LPC845M301JHI48 hvqfn48 hvqfn: plastic thermal enha nced very thin quad flat package; no leads; 48 terminals; body 7 ? 7 ? 0.85 mm sot619-1 lpc845m301jhi33 hvqfn33 hvqfn: plastic thermal enha nced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm sot617-11 lpc844m201jbd64 lqfp64 plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc844m201jbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc844m201jhi48 hvqfn48 hvqfn: plastic thermal enha nced very thin quad flat package; no leads; 48 terminals; body 7 ? 7 ? 0.85 mm sot619-1 lpc844m201jhi33 hvqfn33 hvqfn: plastic thermal enha nced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm sot617-11 table 2. ordering options type number flash/kb sram/kb usart i 2 c spi dac capacitive touch gpio package lpc845m301jbd64 64 16 5 4 2 2 yes 54 lqfp64 lpc845m301jbd48 64 16 5 4 2 2 yes 42 lqfp48 LPC845M301JHI48 64 16 5 4 2 2 yes 42 hvqfn48 lpc845m301jhi33 64 16 5 4 2 1 - 29 hvqfn33 lpc844m201jbd64 64 8 2 2 2 - - 54 lqfp64 lpc844m201jbd48 64 8 2 2 2 - - 42 lqfp48 lpc844m201jhi48 64 8 2 2 2 - - 42 hvqfn48 lpc844m201jhi33 64 8 2 2 2 - - 29 hvqfn33
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 5 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 5. marking the lpc84x lqfp64 and lqfp48 packag es have the following top-side marking: ? first line: lpc84xmy01 ? y: 3 or 2 ? second line: xxxxxx ? third line: xxxyywwx[r]x ? yyww: date code with yy = year and ww = week. ? xr = boot code version and device revision. the lpc84x hvqfn48 and hvqfn33 packages have the following top-side marking: ? first line: lpc84xmy01 ? y: 3 or 2 ? second line: xxxxxx ? third line: xxxyywwx[r]x ? yyww: date code with yy = year and ww = week. ? xr = boot code version and device revision. fig 1. hvqfn48, hvqfn33 package marking fig 2. lqfp64, lqfp48 package marking aaa-014382 terminal 1 index area nxp 1 n terminal 1 index area aaa-011231 table 3. device revision table revision identifier (r) revision description 1a initial device revision with boot rom version 13.1
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 6 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 6. block diagram gray-shaded blocks show peripherals that can provide hardware triggers or fi xed dma requests for dma transfers. fig 3. lpc84x block diagram aaa-022793 clkout vdd clkin xtalin xtalout swd port jtag test and boundary scan interface reset clock generation, power control, and other system functions voltage regulator debug interface iop bus gpios gpios and gpoint flash interface flash 64 kb general purpose dma controller mtb slave interface dma registers crc multilayer ahb matrix ahb to apb bridge faim 256-bit t0 match/ capture p0 m1 m0 p1 p2 p4 p3 i2c2,3 comp inputs adc inputs and triggers dac1 outputs dac0 outputs pios uart0,1,2, 3,4 capt spi0,1 i2c0,1 apb slave group watchdog osc windowed wdt note: sct timer/ pwm arm cortex m0+ system control iocon registers flash registers (nvmc) ctimer32 i2cs 2 and 3 uarts 0-4 captouch spis 0 and 1 i2cs 0 and 1 periph input mux selects comparator pmu registers 12-bit adc 10-bit dac1 10-bit dac0 faim registers switch matrix wakeup timer multi-rate timer boot rom 16 kb sram/mtb 8 kb sram 8 kb yellow shaded blocks support general purpose dma
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 7 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 7. pinning information 7.1 pinning fig 4. pin configuration lqfp64 package pio1_8/capt_yl pio0_0/acmp_ i1/tdo pio0_13/adc_10 pio1_7/capt_x8 pio1_9/capt_yh pio0_6/adc_1/acmpv ref pio0_12 pio0_7/adc_0 pio0_5/reset pio1_19 pio0_4/adc_11/trst/wakeup pio1_18 v dd vrefp v ss vrefn pio1_12 v ss v dd pio0_28/wktclkin pio1_6/capt_x7 pio1_13 pio1_17 swclk/pio0_3/tck pio1_16 pio0_31/capt_x0 pio1_5/capt_6 pio1_0/capt_x1 pio0_8/xtalin pio0_11/i2c0_sda pio0_9/xtalout pio0_10/i2c0_scl pio1_10 pio1_1/capt_x2 pio0_17/adc_9/dacout_0 pio0_16 pio1_11 pio1_2/capt_x3 pio0_18/adc_8 pio0_27 pio0_19/adc_7 pio1_14 pio1_21 pio0_26 pio0_20/adc_6 pio1_15 pio0_21/adc_5 v ss pio1_20 v dd pio0_22/adc_4 pio0_25 pio0_30/acmp_i5 pio0_24 v ssa pio1_3/capt_x4 v dda pio0_15 pio0_23/adc_3/acmp_i4 pio1_4/capt_x5 pio0_29/dacout_1 pio0_1/acmp_i2/clkin/tdi pio0_14/acmp_i3/adc_2 aaa-026593 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 swdio/pio0_2/tms
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 8 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 5. pin configuration lqfp48 package pio1_8/capt_yl pio0_0/acmp_i1/tdo pio0_13/adc_10 pio1_7/capt_x8 pio1_9/capt_yh pio0_6/adc_1/acmpv ref pio0_12 pio0_7/adc_0 vrefp pio0_4/adc_11/trst/wakeup vrefn pio0_28/wktclkin v ss swdclk/pio0_3/tck v dd pio0_31/capt_x0 pio1_6/capt_x7 swdio/pio0_2/tms pio1_5/capt_x6 pio1_0/capt_x1 pio0_8/xtalin pio0_11/i2c0_sda pio0_9/xtalout pio0_10/i2c0_scl pio0_17/adc_9/dacout_0 pio1_1/capt_x2 pio0_18/adc_8 pio0_16 pio0_19/adc_7 pio1_2/capt_x3 pio0_20/adc_6 pio0_27 pio0_21/adc_5 pio0_26 pio0_22/adc_4 pio0_25 pio0_30/acmp_i5 pio0_24 vssa pio1_3/capt_x4 vdda pio0_15 pio0_23/adc_3/acmp_i4 pio1_4/capt_x5 pio0_1/acmp_i2/clkin/tdi pio0_29/dacout_1 pio0_14/acmp_i3/adc_2 aaa-026594 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 pio0_5/reset
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 9 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 6. pin configuration hvqfn48 package aaa-026596 pio0_9/xtalout pio1_0/capt_x1 pio0_11/i2c0_sda pio0_8/xtalin swdio/pio0_2/tms pio1_5/capt_x6 pio0_31/capt_x0 pio1_6/capt_x7 swdclk/pio0_3/tck vdd pio0_28/wktclkin vss pio0_4/adc_11/trst/wakeup vrefn pio0_5/reset vrefp pio0_12 pio0_7/adc_0 pio1_9/capt_yh pio0_6/adc_1/acmpv ref pio0_13/adc_10 pio1_7/capt_x8 pio1_8/capt_yl pio0_0/acmpin_i1/tdo pio0_10/i2c0_scl pio1_01/capt_x2 pio0_16 pio1_2/capt_x3 pio0_27 pio0_26 pio0_25 pio0_24 pio1_3/capt_x4 pio0_15 pio1_4/capt_x5 pio0_1/acmp_i2/clkin/tdi pio0_17/adc_9/dacout_0 pio0_18/adc_8 pio0_19/adc_7 pio0_20/adc_6 pio0_21/adc_5 pio0_22/adc_4 pio0_30/acmp_i5 vssa vdda pio0_23/adc_3/acmp_i4 pio0_29/dacout_1 pio0_14/adc_2/acmp_i3 transparent top view 12 25 11 26 10 27 9 28 8 29 7 30 6 31 5 32 4 33 3 34 2 35 1 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 terminal 1 index area
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 10 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 7.2 pin description the pin description table shows the pin functions that are fixed to specific pins on each package. see ta b l e 4 . these fixed-pin functions are selectable through the switch matrix between gpio and the comp arator, adc, swd, reset , and the xtal pins. by default, the gpio function is selected except on pins pio0_2, pio0_3, and pio0_5. jtag functions are available in boundary scan mode only. movable functions for the i 2 c, usart, spi, ctimer, sct pins, and other peripherals can be assigned through the switch matrix to any pin that is not power or ground in place of the pin?s fixed functions. the following exceptions apply: do not assign more than one output to any pin. however, an output and/or one or more inputs can be assigned to a pin. once any fu nction is assigned to a pin, the pin?s gpio functionality is disabled. pin pio0_4 triggers a wake-up from deep power-down mode. if the part must wake up from deep power-down mode via an external pi n, do not assign any movable function to this pin. fig 7. pin configuration hvqfn33 package aaa-026595 transparent top view pio0_9/xtalout swdio/pio0_2/tms pio0_11/i2c0_sda pio0_8/xtalin swclk/pio0_3/tck vdd pio0_28/wktclkin vrefn pio0_4/adc_11/trst/wakeup vrefp pio0_5/reset pio0_7/adc_0 pio0_12 pio0_6/adc_1/acmpv ref pio0_13/adc_10 pio0_0/acmp_i1/tdo pio0_10/i2c0_scl pio0_16 pio0_27 pio0_26 pio0_25 pio0_24 pio0_15 pio0_1/acmp_i2/clkintdi pio0_17/adc_9/dacout_0 pio0_18/adc_8 pio0_19/adc_7 pio0_20/adc_6 pio0_21/adc_5 pio0_22/adc_4 pio0_23/adc_3/acmp_i4 pio0_14/acmp_i3/adc_2 8 17 7 18 6 19 5 20 21 3 4 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 11 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller pio0_10 and pio_11 are high current source pins while pio0_2, pio0_3, pio0_12, and pio0_16 are high drive output pins. the jtag functions tdo, tdi, tck, tms, and trst are selected on pins pio0_0 to pio0_4 by hardware when the part is in boundary scan mode. table 4. pin description symbol lqfp64 lqfp48 hvqfn48 hvqfn33 reset state [1] type description pio0_0/acmp_i1/ tdo 48 36 36 24 [2] i; pu io pio0_0 ? general-purpose port 0 input/output 0. in boundary scan mode: tdo (test data out). a acmp_i1 ? analog comparator input 1. pio0_1/acmp_i2/ clkin/tdi 32 24 24 16 [2] i; pu io pio0_1 ? general-purpose port 0 input/output 1. in boundary scan mode: tdi (test data in). a acmp_i2 ? analog comparator input 2. i clkin ? external clock input. swdio/pio0_2/ tms 14 10 10 7 [4] i; pu io swdio ? serial wire debug i/o. swdio is enabled by default on this pin. in boundary scan mode: tms (test mode select). i/o pio0_2 ? general-purpose port 0 input/output 2. swclk/pio0_3/ tck 12 8 8 6 [4] i; pu i swclk ? serial wire clock. sw clk is enabled by default on this pin. in boundary scan mode: tck (test clock). io pio0_3 ? general-purpose port 0 input/output 3. pio0_4/adc_11/ trstn/wakeup 6664 [3] i; pu io pio0_4 ? general-purpose port 0 input/output 4. in boundary scan mode: trst (test reset). this pin triggers a wake-up from deep power-down mode. if the part must wake up from deep power-down mode via the wakeup pin, do not assign any movable function to this pin and must be externally pulled high before entering deep power-down mode. a low-going pulse as short as 50 ns causes the chip to exit deep power-down mode and wakes up the part. the wakeup pin can be left unconnected or be used as a gpio or for any movable function if an external wakeup function is not needed. a adc_11 ? adc input 11.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 12 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller reset /pio0_5 5 5 5 3 [7] i; pu i reset ? external reset input: a low-going pulse (minimum 20 ns to maximum 50 ns) on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. this pin triggers a wake-up from deep power-down mode. if the part must wake up from deep power-down mode via the reset pin, do not assign any movable function to this pin and must be externally pulled high before entering deep power-down mode. the reset pin can be left unconnected or be used as a gpio or for any movable function if an external reset function is not needed. io pio0_5 ? general-purpose port 0 input/output 5. pio0_6/adc_1/ acmpv ref 46 34 34 23 [10] i; pu io pio0_6 ? general-purpose port 0 input/output 6. a adc_1 ? adc input 1. a acmpv ref ? alternate reference voltage for the analog comparator. pio0_7/adc_0 45 33 33 22 [2] i; pu io pio0_7 ? general-purpose port 0 input/output 7. a adc_0 ? adc input 0. pio0_8/xtalin 34 26 26 18 [8] i; pu io pio0_8 ? general-purpose port 0 input/output 8. a xtalin ? input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.95 v in slave mode. see section 14.2.2 ? xtal input ? . pio0_9/xtalout 33 25 25 17 [8] i; pu io pio0_9 ? general-purpose port 0 input/output 9. a xtalout ? output from the oscillator circuit. pio0_10/i2c0_scl 17 13 13 9 [6] inactive i; f pio0_10 ? general-purpose port 0 input/output 10 (open-drain). i2c0_scl ? open-drain i 2 c-bus clock input/output. high-current sink if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_11/i2c0_sda 16 12 12 8 [6] inactive i; f pio0_11 ? general-purpose port 0 input/output 11 (open-drain). i2c0_sda ? open-drain i 2 c-bus data input/output. high-current sink if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_12 4 4 4 2 [4] i; pu io pio0_12 ? general-purpose port 0 input/output 12. isp entry pin. a low level on this pin during reset starts the isp command handler. pio0_13/adc_10 2 2 2 1 [2] i; pu io pio0_13 ? general-purpose port 0 input/output 13. a adc_10 ? adc input 10. table 4. pin description symbol lqfp64 lqfp48 hvqfn48 hvqfn33 reset state [1] type description
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 13 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller pio0_14/ acmp_i3/adc_2 49 37 37 25 [2] i; pu io pio0_14 ? general-purpose port 0 input/output 14. a acmp_i3 ? analog comparator common input 3. a adc_2 ? adc input 2. pio0_15 30 22 22 15 [5] i; pu io pio0_15 ? general-purpose port 0 input/output 15. pio0_16 19 15 15 10 [4] i; pu io pio0_16 ? general-purpose port 0 input/output 16. pio0_17/adc_9/ dacout_0 63 48 48 32 [2] i; pu io pio0_17 ? general-purpose port 0 input/output 17. a adc_9 ? adc input 9. a dacout_0 ? dac output 0. pio0_18/adc_8 61 47 47 31 [2] i; pu io pio0_18 ? general-purpose port 0 input/output 18. a adc_8 ? adc input 8. pio0_19/adc_7 60 46 46 30 [2] i; pu io pio0_19 ? general-purpose port 0 input/output 19. a adc_7 ? adc input 7. pio0_20/adc_6 58 45 45 29 [2] i; pu io pio0_20 ? general-purpose port 0 input/output 20. a adc_6 ? adc input 6. pio0_21/adc_5 57 44 44 28 [2] i; pu io pio0_21 ? general-purpose port 0 input/output 21. a adc_5 ? adc input 5. pio0_22/adc_4 55 43 43 27 [2] i; pu io pio0_22 ? general-purpose port 0 input/output 22. a adc_4 ? adc input 4. pio0_23/adc_3/ acmp_i4 51 39 39 26 [2] i; pu io pio0_23 ? general-purpose port 0 input/output 23. a adc_3 ? adc input 3. a acmp_i4 ? analog comparator common input 4. pio0_24 28 20 20 14 [5] i; pu io pio0_24 ? general-purpose port 0 input/output 24. in isp mode, this is the u0_rxd pin. pio0_25 27 19 19 13 [5] i; pu io pio0_25 ? general-purpose port 0 input/output 25. in isp mode, this pin is the u0_txd pin. pio0_26 23 18 18 12 [5] i; pu io pio0_26 ? general-purpose port 0 input/output 26. pio0_27 21 17 17 11 [5] i; pu io pio0_27 ? general-purpose port 0 input/output 27. pio0_28/ wktclkin 10 7 7 5 [3] i; pu io pio0_28 ? general-purpose port 0 input/output 28. this pin can host an external clock for the self-wake-up timer. to use the pin as a self-wake-up timer clock input, select t he external clock in the wake-up timer ctrl register. the external clock input is active in all power modes, including deep power-down. pio0_29/ dacout_1 50 38 38 - [5] i; pu io pio0_29 ? general-purpose port 0 input/output 29. a dacout_1 ? dac output 1. pio0_30/acmp_i5 54 42 42 - [5] i; pu io pio0_30 ? general-purpose port 0 input/output 30. a acmp_i5 ? analog comparator common input 5. table 4. pin description symbol lqfp64 lqfp48 hvqfn48 hvqfn33 reset state [1] type description
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 14 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller pio0_31/capt_x0 13 9 9 - [5] i; pu io pio0_31 ? general-purpose port 0 input/output 31. capt_x0 ? capacitive touch x sensor 0. pio1_0/capt_x1 15 11 11 - [5] i; pu io pio1_0 ? general-purpose port 1 input/output 0. capt_x1 ? capacitive touch x sensor 1. pio1_1/capt_x2 18 14 14 - [5] i; pu io pio1_1 ? general-purpose port 1 input/output 1. capt_x2 ? capacitive touch x sensor 2. pio1_2/capt_x3 20 16 16 - [5] i; pu io pio1_2 ? general-purpose port 1 input/output 2. capt_x3 ? capacitive touch x sensor 3. pio1_3/capt_x4 29 21 21 - [5] i; pu io pio1_3 ? general-purpose port 1 input/output 3. capt_x4 ? capacitive touch x sensor 4. pio1_4/capt_x5 31 23 23 - [5] i; pu io pio1_4 ? general-purpose port 1 input/output 4. capt_x5 ? capacitive touch x sensor 5. pio1_5/capt_x6 35 27 27 - [5] i; pu io pio1_5 ? general-purpose port 1 input/output 5. capt_x6 ? capacitive touch x sensor 6. pio1_6/capt_x7 38 28 28 - [5] i; pu io pio1_6 ? general-purpose port 1 input/output 6. capt_x7 ? capacitive touch x sensor 7. pio1_7/capt_x8 47 35 35 - [5] i; pu io pio1_7 ? general-purpose port 1 input/output 7. capt_x8 ? capacitive touch x sensor 8. pio1_8/capt_yl 1 1 1 - [5] i; pu io pio1_8 ? general-purpose port 1 input/output 8. capt_yl ? capacitive touch y low. pio1_9/capt_yh 3 3 3 - [5] i; pu io pio1_9 ? general-purpose port 1 input/output 9. capt_yh ? capacitive touch y high. pio1_10 64 - - - [5] i; pu io pio1_10 ? general-purpose port 1 input/output 10. pio1_11 62 - - - [5] i; pu io pio1_11 ? general-purpose port 1 input/output 11. pio1_12 9 - - - [5] i; pu io pio1_12 ? general-purpose port 1 input/output 12. pio1_13 11 - - - [5] i; pu io pio1_13 ? general-purpose port 1 input/output 13. pio1_14 22 - - - [5] i; pu io pio1_14 ? general-purpose port 1 input/output 14. pio1_15 24 - - - [5] i; pu io pio1_15 ? general-purpose port 1 input/output 15. pio1_16 36 - - - [5] i; pu io pio1_16 ? general-purpose port 1 input/output 16. pio1_17 37 - - - [5] i; pu io pio1_17 ? general-purpose port 1 input/output 17. pio1_18 43 - - - [5] i; pu io pio1_18 ? general-purpose port 1 input/output 18. pio1_19 44 - - - [5] i; pu io pio1_19 ? general-purpose port 1 input/output 19. pio1_20 56 - - - [5] i; pu io pio1_20 ? general-purpose port 1 input/output 20. pio1_21 59 - - - [5] i; pu io pio1_21 ? general-purpose port 1 input/output 21. v dd 7;26;39 29 29 19 - - supply voltage for the i/o pad ring, the and core voltage regulator. v dda 52 40 40 analog supply voltage. v ss 8;25;40 30 30 33 [11] - - ground. table 4. pin description symbol lqfp64 lqfp48 hvqfn48 hvqfn33 reset state [1] type description
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 15 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller [1] pin state at reset for default function: i = input; ai = anal og input; o = output; pu = internal pull-up enabled (pins pulle d up to full v dd level); ia = inactive, no pull-up/down enabled; f = floati ng. for pin states in the different power modes, see section 14.6 ? pin states in different power modes ? . for termination on unused pins, see section 14.5 ? termination of unused pins ? . [2] 5 v tolerant pin providing standard digita l i/o functions with configurable modes, configurable hysteresis, and analog input . when configured as an analog input, the digital section of t he pin is disabled, and the pin is not 5 v tolerant. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. this pin is active in deep power-down mode and includes a 20 ns glitch filter (active in all power modes). in deep power-down mode, pulling the wakeup pin low wakes up the chip. the wake-up pin function can be disabled and the pin can be used for other purposes, if the wkt low-power oscillator is enabled for waking up the part from deep power-down mode. see table 20 ? dynamic characteristics: wktclkin pin ? for the wktclkin input. [4] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis; includes high-current output driver. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [6] true open-drain pin. i 2 c-bus pins compliant with the i 2 c-bus specification for i 2 c standard mode, i 2 c fast-mode, and i 2 c fast-mode plus. do not use this pad for high-speed appl ications such as spi or usart. the pi n requires an external pull-up to provide out put functionality. when power is switched off, this pin is floating and does not disturb the i2c lines. open-drain configuration ap plies to all functions on this pin. [7] see figure 14 for the reset pad configuration. this pin includes a 20 ns glitch filter (active in all power modes). reset functionality is available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. [8] 5 v tolerant pin providing standard digital i/o functions wi th configurable modes, configur able hysteresis, and analog i/o f or the system oscillator. when configured for xtalin and xtalout, the digital se ction of the pin is disabled, and the pin is not 5 v tolerant . [9] the wktclkin function is enabled in the dpdctrl re gister in the pmu. see the lpc84x user manual. [10] the digital part of this pin is 3 v tolerant pin due to s pecial analog functionality. pin pr ovides standard digital i/o fun ctions with configurable modes, confi gurable hysteresis, and an analog input. when configur ed as an analog input, the digital section of th e pin is disabled. [11] thermal pad for hvqfn33. v ssa 53 41 41 analog ground. vrefn 41 31 31 20 - - adc negative reference voltage. vrefp 42 32 32 21 - - adc positive reference voltage. must be equal or lower than v dda . table 4. pin description symbol lqfp64 lqfp48 hvqfn48 hvqfn33 reset state [1] type description table 5. movable functions (assign to pins pio 0_0 to pio0_31, pio1_0 to pio1_21 through switch matrix) function name type description ux_txd o transmitter output for usart0 to usart4. ux_rxd i receiver input fo r usart0 to usart4. ux_rts o request to send output for usart0 to usart4. ux_cts i clear to send input for usart0 to usart4. ux_sclk i/o serial clock input/output for usart0 to usart4 in synchronous mode. spix_sck i/o serial clock for spi0 and spi1. spix_mosi i/o master out slave in for spi0 and spi1. spix_miso i/o master in slave out for spi0 and spi1.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 16 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller spix_ssel0 i/o slave select 0 for spi0 and spi1. spix_ssel1 i/o slave select 1 for spi0 and spi1. spix_ssel2 i/o slave select 2 for spi0 and spi1. spix_ssel3 i/o slave select 3 for spi0 and spi1. sct_pin0 i pin input 0 to the sct input multiplexer. sct_pin1 i pin input 1 to the sct input multiplexer. sct_pin2 i pin input 2 to the sct input multiplexer. sct_pin3 i pin input 3 to the sct input multiplexer. sct_out0 o sct output 0. sct_out1 o sct output 1. sct_out2 o sct output 2. sct_out3 o sct output 3. sct_out4 o sct output 4. sct_out5 o sct output 5. i2cx_sda i/o i 2 c1, i 2 c2, and i 2 c3 bus data input/output. i2cx_scl i/o i 2 c1, i 2 c2, and i 2 c3 bus clock input/output. acmp_o o analog comparator output. clkout o clock output. gpio_int_bmat o output of the pattern match engine. t0_mat0 o timer match channel 0. t0_mat1 o timer match channel 1. t0_mat2 o timer match channel 2. t0_mat3 o timer match channel 3. t0_cap0 i timer capture channel 0. t0_cap1 i timer capture channel 1. t0_cap2 i timer capture channel 2. table 5. movable functions (assign to pins pio 0_0 to pio0_31, pio1_0 to pio1_21 through switch matrix) function name type description
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 17 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8. functional description 8.1 arm cortex-m0+ core the arm cortex-m0+ core runs at an operating frequency of up to 30 mhz using a two-stage pipeline. the core revision is r0p1. integrated in the core are th e nvic and serial wire debug with four breakpoints and two watchpoints. the arm cortex-m0+ core supports a single-cycle i/o enabled port for fast gpio access. the core includes a single-cycle multiplier and a system tick timer. 8.2 on-chip flash program memory the lpc84x contain up to 64 kb of on-c hip flash program memory. the flash memory supports a 64 byte page size with page write and erase. 8.3 on-chip sram the lpc84x contain a total of 16kb on-chip static ram data memory in two separate sram blocks with one combined clock for both sram blocks. one 8 kb of sram can be used for mtb. a bit-band module is added in series with the ahb matrix to allow atomic read-modify-write operations acting on a single bit. 8.4 faim memory the lpc84x includes the faim memory and is us ed to configure the part at start-up. it is 128/256 bits in size and is used to configure the following: ? clocks and pmu for lo w-power start-up. ? low power boot at 1.5 mhz using faim memory. ? pin configuration including direction and pull- up or pull-down. ? specification of pins to use for isp entry for each serial peripheral. ? select whether swclk and swdio are enabled on reset. remark: the faim programming voltage range is 3.0 v ? vdd ? 3.6 v. 8.5 on-chip rom the on-chip rom contains the bootloader: ? boot loader. ? supports flash in-application programming (iap). ? supports in-system programming (isp) through usart, spi, and i 2 c. ? on-chip rom apis for integer divide. ? faim api. ? fro api.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 18 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8.6 memory map the lpc84x incorporates seve ral distinct memory regions. figure 8 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the arm private pe ripheral bus includes the arm core registers for controlling the nvic, the system tick timer (systick), and the reduced power modes. fig 8. lpc84x ahb memory mapping aaa-026589 faim memory mtb registers dma controller sctimer / pwm ahb perpherals crc engine 0x5001 4000 0x5001 0000 0x5000 c000 0x5000 8000 0x5000 4000 0x5000 0000 (reserved) private peripheral bus (reserved) gpio interrupts memory space gpio (reserved) (reserved) (reserved) (reserved) (reserved) active interrupt vectors boot rom ram1 ram0 ahb peripherals apb peripherals flash memory (up to 64 kb) 0xffff ffff 0xe010 0000 0xe000 0000 0xa000 8000 0xa000 4000 0xa000 0000 0x5001 4000 0x5000 0000 0x4008 0000 0x4000 0000 0x1000 4000 0x1000 2000 0x1000 0000 0x0f00 4000 0x0f00 0000 0x0001 0000 0x0000 0000 0x0000 00c0 0x0000 0000 (reserved) uart4 uart3 uart2 apb perpherals uart1 uart0 captouch spi1 spi0 i2c1 i2c0 (reserved) syscon iocon flash controller (reserved) ctimer 0 i2c3 i2c2 input multiplexing (reserved) analog comparator pmu adc dac1 dac0 faim controller switch matrix wake-up timer multi-rate timer watchdog timer 31-30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x4007 ffff 0x4007 8000 0x4007 4000 0x4007 0000 0x4006 c000 0x4006 8000 0x4006 4000 0x4006 0000 0x4005 c000 0x4005 8000 0x4005 4000 0x4005 0000 0x4004 c000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 c000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 c000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 c000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 c000 0x4000 8000 0x4000 4000 0x4000 0000
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 19 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8.7 nested vectored inte rrupt controller (nvic) the nested vectored interrupt controller (nvi c) is part of the cortex-m0+. the tight coupling to the cpu allows for lo w interrupt latency and efficient processing of late arriving interrupts. 8.7.1 features ? nested vectored interrupt controller is a part of the arm cortex-m0+. ? tightly coupled interrupt controller provides low interrupt latency. ? controls system exceptions and peripheral interrupts. ? supports 32 vectored interrupts. ? in the lpc84x, the nvic supports vectored interrupts for each of the peripherals and the eight pin interrupts. ? four programmable interrupt priority levels with hardware prio rity level masking. ? software interrupt generation using the arm exceptions svcall and pendsv. ? supports nmi. 8.7.2 interrupt sources each peripheral device has at least one interr upt line connected to the nvic but can have several interrupt flags. individual interrupt flags can also represent more than one interrupt source. 8.8 system tick timer the arm cortex-m0+ includes a 24-bit system tick timer (systick) that is intended to generate a dedicated systick exception at a fixed time interval (typically 10 ms). 8.9 i/o configuration the iocon block controls the configuration of the i/o pins. each digital or mixed digital/analog pin with the pio0_n designato r (except the true open-drain pins pio0_10 and pio0_11) in ta b l e 4 can be configured as follows: ? enable or disable the weak internal pull-up and pull-down resistors. ? select a pseudo open-drain mode. the input cannot be pulled up above v dd . the pins are not 5 v tolerant when v dd is grounded. ? program the input glitch filter with differ ent filter constants using one of the iocon divided clock signals (ioconclkcdiv, see figure 11 ? lpc84x clock generation ? ). you can also bypass the glitch filter. ? invert the input signal. ? hysteresis can be en abled or disabled. ? for pins pio0_10 and pio0_11, select the i2c-mode and output driver for standard digital operation, for i2c standard and fast modes, or for i2c fast mode+. ? the switch matrix setting enables the analog input mode on pins with analog and digital functions. enabling the analog mo de disconnects the digital functionality. remark: the functionality of each i/o pin is flexib le and is determined entirely through the switch matrix. see section 8.10 for details.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 20 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8.9.1 standard i/o pad configuration figure 9 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver with conf igurable open-drain output. ? digital input: weak pull-up resistor (pmos device) enabled/disabled. ? digital input: weak pull-down resistor (nmos device) enabled/disabled. ? digital input: repeater mode enabled/disabled. ? digital input: programmable input digital filter selectable on all pins. ? analog input: selected through the switch matrix. fig 9. standard i/o pad configuration pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input analog input swm pinenable for analog input pin configured as digital output driver pin configured as digital input pin configured as analog input programmable digital filter aaa-014392
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 21 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8.10 switch matrix (swm) the switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowin g to connect many functions, for example, the usart, spi, sctimer/pwm, ctimer, and i 2 c functions to any pin that is not power or ground. these functions are called movable functions and are listed in ta b l e 5 . functions that need sp ecialized pads like the oscillato r pins xtalin and xtalout can be enabled or disabled through the switch matrix. these functions are called fixed-pin functions and cannot move to other pins. the fixed-pin functions are listed in ta b l e 4 . if a fixed-pin function is disabled, any other mov able function can be assigned to this pin. 8.11 fast general-purpo se parallel i/o (gpio) device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. lpc84x use accelerated gpio functions: ? gpio registers are on the arm cortex-m0+ io bus for fastest possible single-cycle i/o timing, allowing gpio toggling wi th rates of up to 15 mhz. ? an entire port value can be written in one instruction. ? mask, set, and clear operations are supported for the entire port. all gpio port pins are fixed-pi n functions that are enabled or disabled on the pins by the switch matrix. therefore each gpio port pin is assigned to one specific pin and cannot be moved to another pin. except for pi ns swdio/pio0_2, swclk/pio0_3, and reset /pio0_5, the switch matrix enables the gpio port pin function by default. 8.11.1 features ? bit level port registers allow a single instruction to set and clear any number of bits in one write operation. ? direction control of individual bits. ? all i/o default to gpio inputs with internal pull-up resistors enabled after reset - except for the i 2 c-bus true open-drain pins pio0_10 and pio0_11. ? pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the iocon block for each gpio pin (see figure 9 ). ? direction (input/output) can be set and cleared individually. ? pin direction bits can be toggled. 8.12 pin interrupt/pattern match engine the pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the nvic. the pattern match engine can be used, with software, to create complex state machines based on pin inputs.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 22 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller any digital pin, independently of the function selected through the switch matrix, can be configured through the syscon block as input to the pin interrupt or pattern match engine. the registers that control the pin interrupt or pattern match engine are on the io+ bus for fast single-cycle access. 8.12.1 features ? pin interrupts ? up to eight pins can be selected from all digital pins as edge- or level-sensitive interrupt requests. each request creates a separate interrupt in the nvic. ? edge-sensitive interrupt pins can interrup t on rising or falling edges or both. ? level-sensitive interrupt pins can be high- or low-active. ? pin interrupts can wake up the lpc84x from sleep mode, deep-sleep mode, and power-down mode. ? pin interrupt pattern match engine ? up to eight pins can be selected from all digital pins to contribute to a boolean expression. the boolean expression consists of specified levels and/or transitions on various combinations of these pins. ? each minterm (product term) comprising the specified boolean expression can generate its own, dedicated interrupt request. ? any occurrence of a pattern match can be also programmed to generate an rxev notification to the arm cpu. the r xev signal can be connected to a pin. ? the pattern match engine d oes not facilitate wake-up. 8.13 dma controller the dma controller can access all memories and the usart, spi, i 2 c, dac, and capacitive touch. dma transfers can also be triggered by internal events like the adc interrupts, the pin interrupts (pinint0 and pinint1), the sctimer dma requests, ctimer, and the dma trigger outputs. 8.13.1 features ? twenty five channels with each channel connected to peripheral request inputs. ? dma operations can be triggered by on-chip events or by two pin interrupts. each dma channel can select one trigger input from13 sources. ? priority is user selectable for each channel. ? continuous priority arbitration. ? address cache with two entries. ? efficient use of data bus. ? supports single transfers up to 1,024 words. ? address increment options allow packing and/or unpacking data.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 23 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8.13.2 dma trigger input mux (trigmux) each dma trigger is connected to a programma ble multiplexer which connects the trigger input to one of multiple trig ger sources. each multiplexe r supports the same trigger sources: the adc sequence interrupts, the sct dma request lines, and pin interrupts pinint0 and pinint1, and the outputs of th e dma triggers 0 and 1 for chaining dma triggers. 8.14 usart0/1/2/3/4 all usart functions are movable functions a nd are assigned to pins through the switch matrix. 8.14.1 features ? maximum bit rates of 1.875 mbit/s in asynchronous mode and 10 mbit/s in synchronous mode for usart functions conn ected to all digital pins except the open-drain pins. ? 7, 8, or 9 data bits and 1 or 2 stop bits ? synchronous mode with master or slave operation. includes data phase selection and continuous clock option. ? multiprocessor/multidrop (9-bit) mode with software address compare. (rs-485 possible with software address detection and transceiver direction control.) ? parity generation and checking: odd, even, or none. ? one transmit and one receive data buffer. ? rts/cts for hardware signaling for automatic flow control. software flow control can be performed using delta cts detect, transmit disable control, and any gpio as an rts output. ? received data and status can optionally be read from a single register ? break generation and detection. ? receive data is 2 of 3 sample "voting". status flag set when one sample differs. ? built-in baud rate generator. ? a fractional rate divider is shared among all uarts. ? interrupts available for receiver ready, tr ansmitter ready, receiver idle, change in receiver break detect, framing error, pari ty error, overrun, underrun, delta cts detect, and receiver sa mple noise detected. ? separate data and flow control loopback modes for testing. ? baud rate clock can also be output in asynchronous mode. 8.15 spi0/1 all spi functions are movable functions and are assigned to pins through the switch matrix. 8.15.1 features ? maximum data rates of up to 30 mbit/s in master mode and up to 18 mbit/s in slave mode for spi functions connected to all digital pins except the open-drain pins.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 24 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller ? data frames of 1 to 16 bits supported directly. larger frames supported by software. ? master and slave operation. ? data can be transmitted to a slave without the need to read incoming data, which can be useful while setting up an spi memory. ? control information can optionally be writ ten along with data, which allows very versatile operation, including ?any length? frames. ? one slave select input/output with selectable polarity and flexible usage. remark: texas instruments ssi and national microwire modes are not supported. 8.16 i 2 c-bus interface (i 2 c0/1/2/3) the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (f or example, an lcd driver) or a transmitter with the capability to both re ceive and send information (suc h as memory). transmitters and/or receivers can operate in either mast er or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master. the i2c0-bus functions are fixed-pin function s. all other i2c-bus functions for i2c1/2/3 are movable functions and can be assigned through the switch matrix to any pin. however, only the true open-drain pins provi de the electrical characteristics to support the full i2c-bus specification (see ref. 3 ). 8.16.1 features ? i2c0 supports fast-mode plus with data rates of up to 1 mbit/s in addition to standard and fast modes on two true open-drain pins. ? true open-drain pins provide fail-safe operation: when the power to an i 2 c-bus device is switched off, the sda and scl pins connected to the i 2 c0-bus are floating and do not disturb the bus. ? i2c1/2/3 support standard and fast mode with data rates of up to 400 kbit/s. ? independent master, slave, and monitor functions. ? supports both multi-master and multi-master with slave functions. ? multiple i 2 c slave addresses supported in hardware. ? one slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple i 2 c bus addresses. ? 10-bit addressing supported with software assist. ? supports smbus. 8.17 capacitive touch interface the capacitive touch interface is designed to handle up to nine capacitive buttons in different sensor configurations, such as sli der, rotary, and button matrix. it operates in sleep, deep sleep, and power-down mode s, allowing very low power performance.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 25 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller the capacitive touch module measures the change in capacitance of an electrode plate when an earth-ground connected object (for example, finger) is brought within close proximity. 8.18 sctimer/pwm the sctimer/pwm can perform basic 16-bit a nd 32-bit timer/counter functions with match outputs and external and internal capture inputs. in addition, the sctimer/pwm can employ up to eight different programmable st ates, which can change under the control of events, to provide co mplex timing patterns. the inputs to the sct are multiplexed betwe en movable functions from the switch matrix and internal connections such as the adc threshold compare interrupt, the comparator output, and the arm core signals arm_txev and debug_halted. the signal on each sct input is selected through the input mux. all outputs of the sct are movable functions and are assigned to pins through the switch matrix. one sct output can also be selected as one of the adc conversion triggers. 8.18.1 features ? each sctimer/pwm supports: ? eight match/capture registers. ? eight events. ? eight states. ? five inputs. the fifth input is hard-wired to a clock source. each input is configurable through an input multiplexer to use one of four external pins (connected through the switch matrix) or one of four internal sources. the maximum input signal frequency is 25 mhz. ? six outputs. connected to pins through the switch matrix. ? counter/timer features: ? each sctimer is configurable as two 16-bit counters or one 32-bit counter. ? counters can be clocked by the system clock or selected input. ? configurable as up counters or up-down counters. ? configurable number of match and capture registers. up to eight match and capture registers total. ? upon match create the following events: inte rrupt; stop, limit, halt the timer or change counting direction; toggle outputs. ? counter value can be loaded into capture register triggered by a match or input/output toggle. ? pwm features: ? counters can be used with match regist ers to toggle outputs and create time-proportioned pwm signals. ? up to six single-edge or dual-edge pwm outputs with independent duty cycle and common pwm cycle length. ? event creation features:
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 26 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller ? the following conditions define an event: a counter match condition, an input (or output) condition such as a rising or fallin g edge or level, a combination of match and/or input/output condition. ? selected events can limit, halt, start, or stop a counter or change its direction. ? events trigger state changes, output togg les, interrupts, and dma transactions. ? match register 0 can be used as an automatic limit. ? in bidirectional mode, events can be enabled based on the count direction. ? match events can be held until another qualifying event occurs. ? state control features: ? a state is defined by events that can happen in the state while the counter is running. ? a state changes into another state as a result of an event. ? each event can be assigned to one or more states. ? state variable allows sequencing across multiple counter cycles. ? one sctimer match output can be select ed as adc hardware trigger input. 8.18.2 sctimer/pwm input mux (input mux) each input of the sctimer/pwm is connect ed to a programmable multiplexer which allows to connect one of multiple internal or external sources to the input. the available sources are the same for each sctimer/pwm input and can be selected from four pins configured through the switch matrix, t he adc threshold compare interrupt, the comparator output, and the arm core signals arm_txev and debug_halted. 8.19 ctimer 8.19.1 general-purpose 32-bit timers/external event counter the lpc84x has one general-purpose 32-bit timer/counter. the timer/counter is design ed to count cycles of th e system derived clock or an externally-supplied clock. it can optionally generate interrupts , generate timed dma requests, or perform other actions at spec ified timer values, based on four match registers. each timer/counter al so includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 8.19.2 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation. ? up to three 32-bit captures can take a snapshot of the timer value when an input signal transitions. a capture event may al so optionally generate an interrupt. the number of capture inputs for each timer that are actually available on device pins can vary by device. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 27 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller ? reset timer on match with optional interrupt generation. ? shadow registers are added for glitch-free pwm output. ? for each timer, up to four external outputs corresponding to match registers with the following capabilities (the number of match outputs for each time r that are actually available on device pins can vary by device): ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? up to two match registers can be used to generate timed dma requests. ? the timer and prescaler may be configured to be cleared on a designated capture event. this feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capt uring the timer value on the trailing edge. ? up to four match registers can be configured for pwm operation, allowing up to three single edged controlled pwm outputs. (the number of match outputs for each timer that are actually available on device pins can vary by device.) 8.20 multi-rate timer (mrt) the multi-rate timer (mrt) provides a repetiti ve interrupt timer with four channels. each channel can be programmed with an independent time interval, and each channel operates independently fr om the other channels. 8.20.1 features ? 31-bit interrupt timer ? four channels independently counting down from individually set values ? bus stall, repeat and one-shot interrupt modes 8.21 windowed watc hdog timer (wwdt) the watchdog timer resets the controller if so ftware fails to service the watchdog timer periodically within a programmable time window. 8.21.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect feed sequence causes reset or interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 28 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) is generated by the dedicated watchdog oscillator (wdosc). 8.22 self-wake-up timer (wkt) the self-wake-up timer is a 32-bit, loadable do wn counter. writing any non-zero value to this timer automatically enables the counter and launches a count-down sequence. when the counter is used as a wake-up timer, this write can occur prior to entering a reduced power mode. 8.22.1 features ? 32-bit loadable down counter. counter starts automatically when a count value is loaded. time-out generates an interrupt/wake up request. ? the wkt resides in a separate, always-on power domain. ? the wkt supports three clock sources: an external clock on the wktclkin pin, the low-power oscillator, and the fro. the low-power oscillator is located in the always-on power domain, so it can be used as the clock source in deep power-down mode. ? the wkt can be used for waking up the part from any reduced power mode, including deep power-down mode, or for general-purpose timing. 8.23 analog comparator (acmp) the analog comparator with selectable hysteres is can compare voltage levels on external pins and internal voltages. after power-up and after switching the input chan nels of the comparator , the output of the voltage ladder must be allowed to settle to its stable value before it can be used as a comparator reference input. settling times are given in ta b l e 2 9 . the analog comparator output is a movable fu nction and is assigned to a pin through the switch matrix. the comparator inputs and the voltage reference are enabled through the switch matrix.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 29 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8.23.1 features ? selectable 0 mv, 10 mv ( ? 5 mv), and 20 mv ( ? 10 mv), 40 mv ( ? 20 mv) input hysteresis. ? two selectable external voltages (v dd or acmpv ref ); fully configurable on either positive or negative input channel. ? internal voltage reference from band gap selectable on either positive or negative input channel. ? 32-stage voltage ladder with the internal reference voltage selectable on either the positive or the negative input channel. ? voltage ladder source voltage is selectable from an external pin or the main 3.3 v supply voltage rail. ? voltage ladder can be separa tely powered down for applic ations only requiring the comparator function. ? interrupt outp ut is connected to nvic. ? comparator level output is c onnected to output pin acmp_o. ? one comparator output is internally colle cted to the adc trigger input multiplexer. 8.24 analog-to-digital converter (adc) the adc supports a resolution of 12 bit and fast conversion rates of up to 1.2 msamples/s. sequences of analog-to-digita l conversions can be tr iggered by multiple sources. possible trigger so urces are the pin triggers, the sct output sct_out3, the analog comparator output, and the arm txev. fig 10. comparator block diagram 4 32 4 a cmp_i[5:1] v dd acmpvref dacout_0 internal voltage reference edge detect sync comparator level acmp_o, adc trigger comparator edge nvic comparator analog block comparator digital block aaa-027485
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 30 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller the adc includes a hardware threshold compar e function with zero-crossing detection. remark: for best performance, select vrefp and vrefn at the same voltage levels as v dd and v ss . when selecting vrefp and vrefn different from vdd and vss, ensure that the voltage midpoints are the same: (vrefp-vrefn)/2 + vrefn = v dd /2 8.24.1 features ? 12-bit successive approximation analog to digital converter. ? 12-bit conversion rate of up to 1.2 msamples/s. ? two configurable conversion sequ ences with independent triggers. ? optional automatic high/low threshold comparison and zero-crossing detection. ? power-down mode and low-power operating mode. ? measurement range vrefn to vrefp (not to exceed v dd voltage level). ? burst conversion mode for single or multiple inputs. ? hardware calibration mode. 8.25 digital-to-ana log converter (dac) the dac supports a resolution of 10 bits. conv ersions can be triggered by an external pin input or an internal timer. the dac includes an optional automatic hardware shut-off feature which forces the dac output voltage to zero while a high level on the external dac_shutoff pin is detected. 8.25.1 features ? 10-bit digital-to-analog converter. ? supports dma. ? internal timer or pin external trigger for staged, jitter-free dac conversion sequencing. ? automatic hardware shut-off triggered by an external pin. 8.26 crc engine the cyclic redundancy check (crc) genera tor with programmable polynomial settings supports several crc standards commonl y used. to save system power and bus bandwidth, the crc engine supports dma transfers. 8.26.1 features ? supports three common polynomials crc-ccitt, crc-16, and crc-32. ? crc-ccitt: x 16 + x 12 + x 5 + 1 ? crc-16: x 16 + x 15 + x 2 + 1 ? crc-32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? bit order reverse and 1?s complement programmable setting for input data and crc sum. ? programmable seed number setting.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 31 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller ? supports cpu pio or dma back-to-back transfer. ? accept any size of data width per write: 8, 16 or 32-bit. ? 8-bit write: 1-cycle operation. ? 16-bit write: 2-cycle op eration (8-bit x 2-cycle). ? 32-bit write: 4-cycle operation (8-bit x 4-cycle). 8.27 clocking and power control 8.27.1 crystal and internal oscillators the lpc84x include four independent oscillators: 1. the crystal oscillator (syso sc) operating at frequencie s between 1 mhz and 25 mhz. 2. free running oscillator. 3. watchdog oscillator 4. low power oscillator each oscillator, except th e low-frequency oscillator, c an be used for more than one purpose as required in a particular application. following reset, the lpc84x operates from the fro until switched by software allowing the part to run without any external crystal and the bootloader code to operate at a known frequency. see figure 11 for an overview of the lpc84x clock generation. 8.27.1.1 free running oscillator (fro) the fro oscillator provides the default clock at reset and provides a clean system clock shortly after the supply pins reach operating voltage. ? this oscillator provides a selectable 18 mhz, 24 mhz, and 30 mhz outputs that can be used as a system clock. also, these outputs can be divided down to 1.125 mhz, 1.5 mhz, 1.875 mhz, 9 mhz, 12 mhz, and 15 mhz for system clock. ? the fro is trimmed to 1 % accuracy over the entire voltage and temperature range of 0 c to 70 c. ? by default, the fro_oscout is 24 mhz and is divided by 2 to provide a default system (cpu) clock frequency of 12 mhz. 8.27.1.2 crystal oscillator (sysosc) the crystal oscillator can be used as the clo ck source for the cpu, with or without using the pll. the sysosc operates at fre quencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. 8.27.1.3 internal low-power oscillator and watchdog oscillator (wdosc) the nominal frequency of the wdosc is prog rammable between 9.4 khz and 2.3 mhz. the frequency spread over silicon process variations is ? 40%. the wdosc is a dedicated oscillator for the windowed wwdt.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 32 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller the internal low-power 10 khz ( ? 40% accuracy) oscillator serves as the clock input to the wkt. this oscillator can be configur ed to run in all low-power modes. 8.27.2 clock input an external clock source can be supplied on the selected clkin pin directly to the pll input. when selecting a clock signal for the clki n pin, follow the specifications for digital i/o pins in table 13 ? static characteristics, supply pins ? and table 19 ? dynamic characteristics: i/o pins [1] ? . an 1.8 v external clock source can be su pplied on the xtalin pins to the system oscillator limiting the voltag e of this signal (see section 14.2 ? xtal oscillator ? ). the maximum frequency for both clock signals is 25 mhz. 8.27.3 system pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is provid ing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. since the minimum output divider value is 2, it is insu red that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is nominally 100 ? s. 8.27.4 clock output the lpc84x features a clock output function that routes the fro, the sysosc, the watchdog oscillator, or the main clock to t he clkout function. the clkout function can be connected to any digital pin through the switch matrix.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 33 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 11. lpc84x clock generation aaa-026590 sys_osc_clk fro external_clk wd_osc_clk fro_div external clock select extclksel[0] main clock select mainclksel[1:0] system pll system pll settings sys_pll0_clk clk_in 0 00 01 10 (1) 11 main_clk_pre_pll sys_pll0_clk none none main clock pll select mainclkpllsel ioconclkdiv(i) sysahbclkdiv sysahbclkctrl (one bit per destination) 00 01 10 (1) 11 main_clk main_clk divider to ahb peripherals, ahb matrix, memories, etc. to cpu fro external_clk wdt_osc_clk fro_div pll clock select syspllclksel[1:0] 00 01 10 (1) 11 1 fro main_clk sys_pll0_clk none sct clock select sctclksel[1:0] 00 01 10 11 peripheral_clk divider pin filter(i) sctclkdiv sysahbclkctrl0[sct] sct clock divider to sct input 4 clkoutdiv clkout divider fro sys_pll0_clk none adc clock select adcclksel[1:0] 00 01 11 adcclkdiv adc clock divider to adc fro main_clk sys_pll0_clk fro_div captouch clock select captclksel[2:0] 000 001 010 011 wdt_osc_clk 100 none 111 sysahbclkctrl1[capt] to cap touch fro (1) : synchronized multiplexer, see register desriptions for details. main_clk sys_pll0_clk external_clk clkout select clkoutsel[2:0] 000 001 010 011 wdt_osc_clk 100 none 111 clkout range select and bypass sysoscctrl[1:0] crystal oscillator xtalin xtalout sys_osc_clk
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 34 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 12. lpc84x clock generation (continued) aaa-026591 fro main_clk sys_pll0_clk none frg0 clock select frg0clksel[1:0] frg1 clock select frg1clksel[1:0] frg0div, frg0mult frg1div, frg1mult 00 01 10 11 fro 00 01 10 11 fractional rate divider 0 (frg0) fractional rate divider 1 (frg1) fro main_clk frg0clk frg1clk spln clock select spinclksel[2:0] 000 001 010 011 fro_div 100 none 111 sysahbclkctrl0[spln] one for each spi (spi0 through spi1) to spin fro main_clk frg0clk frg1clk i2cn clock select i2cnclksel[2:0] 000 001 010 011 fro_div 100 none 111 sysahbclkctrl0[i2cn] one for each l2c (i2c0 through i2c3) to i2cn fro main_clk frg0clk frg1clk uartn clock select uartnclksel[2:0] 000 001 010 011 fro_div 100 none 111 sysahbclkctrl0[uartn] one for each uart (uart0 through uart4) to uartn watchdog oscillator wwdt fro oscillator wkt main_clk sys_pll0_clk none
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 35 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8.27.5 power control the lpc84x supports the arm cortex-m0+ sleep mode. the cpu clock rate may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power versus processing speed based on application requirements. in addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing to fine-tune power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. selected peripherals have their ow n clock divider which provides even better power control. fig 13. lpc84x fro subsystem set_fro_frequency() api divide by 2 divide by 8 divide by 2 fro_oscout 30/24/18 mhz (default = 24 mhz) faim word0, low power boot bit frooscctrl[17] fro_direct bit aaa-027256 fro 0 1 0 1 fro oscillator fro_div table 6. clocking diagram si gnal name descriptions name description sys_osc_clk this is the internal clock that comes from external crystal oscillator through dedicated pins. frg_clk the output of the fractional rate generator. the frg and its source selection are shown in figure 12 ? lpc84x clock generation (continued) ? . fro the output of the currently selected on-chip fro oscillator. see um11029 user manual. fro_div the fro output. this may be either 15 mh , 12 mhz, or 9 mhz. see um11029 user manual. main_clk the main clock used by the cpu and ahb bus, and potentially many others. the main clock and its source selection are shown in figure 11 ? lpc84x clock generation ? . ?none? a tied-off source that should be selected to save power when the output of the related multiplexer is not used. sys_pll0_clk the output of the system pll. the system pll and its source selection are shown in figure 11 ? lpc84x clock generation ? . wdt_osc_clk the output of the watchdog osc illator, which has a selectable target frequency. it must also be enabled in the pdrincfg0 register. see um11029 user manual. xtalin input of the main oscillator. if used, this is connected to an external crystal and load capacitor. xtalout output of the main oscillator. if used, this is connected to an external crystal and load capacitor. clk_in this is the internal clock that comes from the main clk_in pin function. connect that function to the pin by selecting it in the iocon block. external_clk this is the internal clock that comes from the external crystal oscillator or the clk_in pin.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 36 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8.27.5.1 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 8.27.5.2 deep-sleep mode in deep-sleep mode, the lpc84x core is in sleep mode and all peripheral clocks and all clock sources are off except for the fro and wa tchdog oscillator or lo w-power oscillator if selected. the fro output is disabled. in addition, all analog blocks are shut down and the flash is in standby mode. in deep-sleep m ode, the application can keep the watchdog oscillator and the bod circuit running for self-timed wake-up and bod protection. the lpc84x can wake up from deep-sleep mo de via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, an interrupt from capacitive touch, or an interrupt from the usart (if the usart is configured in synchronous slave mode), the spi, or the i2c blocks (in slave mode). any interrupt used for waking up from deep-sleep mode must be enabled in one of the syscon wake-up enable r egisters and the nvic. deep-sleep mode saves power and allows for short wake-up times. 8.27.5.3 power-down mode in power-down mode, the lpc84x is in sleep mode and all peripheral clocks and all clock sources are off except for wa tchdog oscillator or low-power oscillator if selected. in addition, all analog blocks and the flash are shut down. in power-down mode, the application can keep the watc hdog oscillator and the bod circ uit running for self-timed wake-up and bod protection. the lpc84x can wake up from power-down mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, an interrupt from capacitive touch, or an interrupt from the usart (if the usart is configured in synchronous slave mode), the spi, or the i2c blocks (in slave mode). any interrupt used for waking up from power-down mode must be enabled in one of the syscon wake-up enable r egisters and the nvic. power-down mode reduces power consumption compared to deep-sleep mode at the expense of longer wake-up times. 8.27.5.4 deep power-down mode in deep power-down mode, power is shut off to the entire chip except for the wakeup pin and the self-wake-up timer. the lpc84x c an wake up from deep power-down mode via the wakeup pin, reset pin, or without an external signal by using the time-out of the self-wake-up timer (see section 8.22 ).
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 37 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller the lpc84x can be prevented from entering deep power-down mode by setting a lock bit in the pmu block. locking out deep power-down mode enables the application to keep the watchdog timer or the bod running at all times. if the part must wake up from deep power-down mode via the wakeup pin or reset pin, do not assign any movable function to th is pin and must be externally pulled high before entering deep power-down mode. table 7. peripheral configuration in reduced power modes peripheral sleep mode deep-sleep mode power-down mode deep power-down mode fro software configurable on off off fro output software configurable off off off flash software configurable on off off bod software configurable software configurable software configurable off pll software configurable off off off sysosc software configurable off off off wdosc/wwdt software co nfigurable software configurable software configurable off digital peripherals software configurable off off off wkt/low-power oscillator software configurable software configurable software configurable software configurable adc software configurable off off off dac0/1 software configurable off off off capacitive touch software configurable software configurable software configurable off comparator software configurable off off off
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 38 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8.27.6 wake-up process the lpc84x begin operation at power-up by using the fro as the clock source allowing chip operation to resume quickl y. if the sysosc, the external clock source, or the pll are needed by the application, software must en able these features and wait for them to stabilize before they are used as a clock source. table 8. wake-up sources for reduced power modes power mode wake-up source conditions sleep any interrupt enable interrupt in nvic. reset pin pio0_5 enable the reset function in the pinenable0 register via switch matrix. deep-sleep and power-down pin interrupts enable pin interrupts in nvic and starterp0 registers. bod interrupt ? enable interrupt in nvic and starterp1 registers. ? enable interrupt in bodctrl register. ? bod powered in pdsleepcfg register. bod reset ? enable reset in bodctrl register. ? bod powered in pdsleepcfg register. wwdt interrupt ? enable interrupt in nvic and starterp1 registers. ? wwdt running. enable wwdt in wwdt mod register and feed. ? enable interrupt in wwdt mod register. ? wdosc powered in pdsleepcfg register. wwdt reset ? wwdt running. ? enable reset in wwdt mod register. ? wdosc powered in pdsleepcfg register. self-wake-up timer (wkt) time-out ? enable interrupt in nvic and starterp1 registers. ? enable low-power oscillator in the dpdctrl register in the pcon block. ? select low-power clock for wkt cl ock in the wkt ctrl register. ? start the wkt by writing a time-out value to the wkt count register. interrupt from usart/spi/i2c peripheral ? enable interrupt in nvic and starterp1 registers. ? enable usart/i2c/spi interrupts. ? provide an external clock signal to the peripheral. ? configure the usart in synchronous slave mode and i2c and spi in slave mode. reset pin pio0_5 enable the reset function in the pinenable0 register via switch matrix. interrupt from capacitive touch peripheral ? enable interrupt in nvic and starterp1 registers. ? enable the capacitive touch interrupt. ? switch fclk clock source to the wdosc. ? set capacitive touch registers. ? provide a touch event to the peripheral. deep power-down wakeup pin pio0_4 enable the wakeup function in the dpdctrl register in the pmu. reset pin pio0_5 enable the reset function in th e dpdctrl register in the pmu to allow wake-up in deep power-down mode. wkt time-out ? enable the low-power oscillator in the dpdctrl register in the pmu. ? enable the low-power oscillator to keep running in deep power-down mode in the dpdctrl register in the pmu. ? select low-power clock for wkt cl ock in the wkt ctrl register. ? start wkt by writing a time-out value to the wkt count register.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 39 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8.28 system control 8.28.1 reset reset has four sources on the lpc84x: the reset pin, the watchdog reset, power-on reset (por), and the brownout detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the fro a nd initializes the flash controller. a low-going pulse as short as 50 ns resets the part. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. in deep power-down mode, an external pull-up resistor is required on the reset pin. 8.28.2 brownout detection the lpc84x includes up to four levels for monitoring the voltage on the v dd pin. if this voltage falls below one of the selected levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for interrupt in the interrupt enable register in the nvic to cause a cpu interrupt. alternatively, so ftware can monitor the signal by reading a dedicated status register. four threshold levels can be selected to cause a forced reset of the chip. fig 14. reset pad configuration 9 66 uhvhw ddd 9 '' 9 '' 9 '' 5 sx (6' (6' qv5& */,7&+),/7(5 3,1
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 40 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8.28.3 code security (code read protection - crp) crp provides different levels of security in th e system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system programming (isp) can be restricted. programming a specific pattern in to a dedicated flash location invokes crp. iap commands are not affected by the crp. in addition, isp entry via the isp entry pi n can be disabled without enabling crp. for details, see the lpc84x user manual . there are three levels of code read protection: 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors cannot be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 selected , fully disables any access to the chip via the swd pins and the isp. this mode ef fectively disables isp override using the isp entry pin as well. if necessary, the application must provide a flash update mechanism using iap calls or using a call to the reinvoke isp command to enable flash update via the usart. in addition to the three crp levels, sampling of the isp entry pin for valid user code can be disabled. for details, see the lpc84x user manual . 8.28.4 apb interface the apb peripherals are located on one apb bus. 8.28.5 ahblite the ahblite connects the cpu bus of the arm cortex-m0+ to the flash memory, the main static ram, the crc, the dma, th e rom, and the apb peripherals. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 41 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 8.29 emulation and debugging debug functions are integrated into the arm cortex-m0+. serial wire debug functions are supported in addition to a standard jt ag boundary scan. the arm cortex-m0+ is configured to support up to four breakpoints and two watch points. the micro trace buffer is implemented on the lpc84x. the reset pin selects between the jtag boundary scan (reset = low) and the arm swd debug (reset = high). the arm swd debug port is disabled while the lpc84x is in reset. the jtag boundary scan pins are selected by hardware when the part is in boundary scan mode (see table 4 ). to perform boundary scan testing, follow these steps: 1. erase any user code residing in flash. 2. power up the part with the reset pin pulled high externally. 3. wait for at least 250 ? s. 4. pull the reset pin low externally. 5. perform boundary scan operations. 6. once the boundary scan operations are completed, assert the trst pin to enable the swd debug mode, and release the reset pin (pull high). remark: the jtag interface cannot be used for debug purposes.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 42 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 9. limiting values table 9. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) [2] ? 0.5 +4.6 v v dda analog supply voltage on pin vdda ? 0.5 +4.6 v v ref reference voltage on pin vrefp ? 0.5 v dd v v i input voltage 5 v tolerant i/o pins; v dd ? 1.8 v [3] [4] ? 0.5 +5.5 v on i2c open-drain pins [5] ? 0.5 +5.5 v 3 v tolerant i/o pin acmpv ref [6] ? 0.5 +3.6 v v ia analog input voltage on digital pins configured for an analog function [7] [8] [9] ? 0.5 +4.6 v v i(xtal) crystal input voltage [2] ? 0.5 +2.5 v i dd supply current per supply pin (lqfp64) - 100 ma per supply pin (lqfp48, hvqfn48) -75 per supply pin (hvqfn33) - 50 i ss ground current per ground pin (lqfp64); - 100 ma per ground pin (lqfp48, hvqfn48) -75 per ground pin (hvqfn33) - 100 i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ? c - 100 ma t stg storage temperature [10] ? 65 +150 ? c t j(max) maximum junction temperature - 150 ? c
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 43 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] maximum/minimum voltage above the maximum operating voltage (see table 13 ) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. failure includes the loss of reli ability and shorter lifetime o f the device. [3] applies to all 5 v tolerant i/o pins except true open-drain pins pio0_10 and pio0_11 and except the 3 v tolerant pin pio0_6. [4] including the voltage on outputs in 3-state mode. [5] v dd present or not present. compliant with the i 2 c-bus standard. 5.5 v can be applied to this pin when v dd is powered down. [6] v dd present or not present. [7] an adc input voltage above 3.6 v can be applied for a short ti me without leading to immediate, unrecoverable failure. accumu lated exposure to elevated voltages at 4.6 v must be less than 10 6 s total over the lifetime of the device. applying an elevated voltage to the adc inputs for a long time affects the reliabili ty of the device and reduces its lifetime. [8] if the comparator is configured with the common mode input v ic = v dd , the other comparator input can be up to 0.2 v above or below v dd without affecting the hysteresis range of the comparator function. [9] it is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [10] dependent on package type. [11] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. [12] jedec (4.5 in ? 4 in); still air. [13] single layer (4.5 in ? 3 in); still air. p tot(pack) total power dissipation (per package) lqfp64, based on package heat transfer, not device power consumption [12] -0.66w lqfp64, based on package heat transfer, not device power consumption [13] -0.48w lqfp48, based on package heat transfer, not device power consumption [12] -0.48w lqfp48, based on package heat transfer, not device power consumption [13] -0.34w hvqfn48, based on package heat transfer, not device power consumption [12] -1.12w hvqfn48, based on package heat transfer, not device power consumption [13] -0.46w hvqfn33, based on package heat transfer, not device power consumption [12] -0.98w hvqfn33, based on package heat transfer, not device power consumption [13] -0.34w v esd electrostatic discharge voltage human body model; all pins - 2000 v table 9. limiting values ?continued in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 44 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 10. thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. t j t amb p d r th j a ? ?? ? ?? + = table 10. thermal resistance symbol parameter conditions max/min unit hvqfn33 package r th(j-a) thermal resistance from junction-to-ambient jedec (4.5 in ? 4 in); still air 40 ? 15 % ? c/w single-layer (4.5 in ? 3 in); still air 114 ? 15 % ? c/w r th(j-c) thermal resistance from junction-to-case 20 ? 15 % ? c/w hvqfn48 package r th(j-a) thermal resistance from junction-to-ambient jedec (4.5 in ? 4 in); still air 35 ? 15 % ? c/w single-layer (4.5 in ? 3 in); still air 85 ? 15 % ? c/w r th(j-c) thermal resistance from junction-to-case 9 ? 15 % ? c/w lqfp48 package r th(j-a) thermal resistance from junction-to-ambient jedec (4.5 in ? 4 in); still air 82 ? 15 % ? c/w single-layer (4.5 in ? 3 in); still air 115 ? 15 % ? c/w r th(j-c) thermal resistance from junction-to-case 30 ? 15 % ? c/w lqfp64 package r th(j-a) thermal resistance from junction-to-ambient jedec (4.5 in ? 4 in); still air 59 ? 15 % ? c/w single-layer (4.5 in ? 3 in); still air 82 ? 15 % ? c/w r th(j-c) thermal resistance from junction-to-case 18 ? 15 % ? c/w
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 45 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 11. static characteristics 11.1 general operating conditions [1] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. [2] including bonding pad capacitance. bas ed on simulation, not tested in production. [3] the v dd supply voltage must be 1.9 v or above when connecting an exter nal crystal oscillator to the system oscillator. if the v dd supply voltage is below 1.9 v, an external clock source can be fed to t he xtalin by bypassing the system oscillator or the other clock sources mentioned above can be used. table 11. general operating conditions t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit f clk clock frequency internal cpu/system clock - - 30 mhz v dd supply voltage (core and external rail) [3] 1.8 - 3.6 v faim programming only 3.0 - 3.6 v for adc operations 2.4 - 3.6 v for dac operations 2.7 - 3.6 v v dda analog supply voltage for adc operations 2.4 - 3.6 v for dac operations 2.7 - 3.6 v v ref adc positive reference voltage on pin vrefp 2.4 - v dda v oscillator pins v i(xtal) crystal input voltage on pin xtalin ? 0.5 1.8 1.95 v v o(xtal) crystal output voltage on pin xtalout ? 0.5 1.8 1.95 v pin capacitance c io input/output capacitance pins with analog and digital functions [2] -- 7.1pf i 2 c-bus pins [2] - - 2.5 pf pins with digital functions only [2] -- 2.8pf
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 46 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 11.2 power-up ramp conditions [1] assert the external reset pin until v dd is > 1.8 v if the power-up char acteristic specif ication cannot be implemented. [2] v dd to stay above v 1 for the entire duration t wd . [3] v dd to stay below v 2 for the minimum duration of t wd . table 12. power-up characteristics [1] t amb = ? 40 ? c to +105 ? c. symbol parameter min typ max unit t wd window duration (time where v 1 lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 47 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 11.3 power consumption power measurements in active, sleep, deep-sleep, and power-down modes were performed under the following conditions: ? configure all pins as gpio with pull-up resistor disabled in the iocon block. ? configure gpio pins as outputs using the gpio dir register. ? write 1 to the gpio clr register to drive the outputs low. [1] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), vdd = 3.3 v. [2] characterized through bench m easurements using typical samples. table 13. static charac teristics, supply pins t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] [2] max [9] unit i dd supply current active mode; code while(1){} executed from flash; system clock = 1.5 mhz; v dd = 3.3 v; low power boot [3] [4] [5] [6] -530- ? a system clock = 12 mhz; v dd = 3.3 v; normal boot [3] [4] [5] [6] -2.0 - ma system clock = 30 mhz; v dd = 3.3 v; normal boot [3] [4] [5] [6] -4.0 - ma sleep mode system clock = 12 mhz; v dd = 3.3 v [3] [4] [5] [6] -1.3 - ma system clock = 30 mhz; v dd = 3.3 v [3] [4] [5] [6] -2.8 - ma i dd supply current deep-sleep mode; v dd = 3.3 v; t amb =25 ? c [3] [7] -240320 ? a t amb =105 ? c--425 ? a i dd supply current power-down mode; v dd = 3.3 v t amb =25 ? c [3] [7] -1.5 10 ? a t amb =105 ? c--70 ? a i dd supply current deep power-down mode; v dd = 3.3 v; 10 khz low-power oscillator and self-wake-up timer (wkt) disabled t amb =25 ? c [8] -0.4 1.0 ? a t amb =105 ? c--4.25 ? a i dd supply current deep power-down mode; v dd = 3.3 v; 10 khz low-power oscillator and self-wake-up timer (wkt) enabled -1.3 - ? a deep power-down mode; v dd = 3.3 v; external clock input wktclkin @ 10 khz with self-wake-up timer enabled -0.43- ? a deep power-down mode; v dd = 3.3 v; external clock input wktclkin @ 32 khz with self-wake-up timer enabled -0.43- ? a
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 48 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller [3] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. [4] fro enabled; system oscillator disabled; system pll disabled. [5] bod disabled. [6] all peripherals disabled in the sysahbclkctrl register. peripheral clocks disabled in system configuration block. [7] all oscillators and analog blocks turned off. [8] wakeup pin pulled high externally. [9] tested in production, vdd = 3.6 v. conditions: bod disabled; all oscillators and analog blocks disabled in the pdsleepcfg register (pdsleepcfg = 0x0000 18ff). fig 16. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd ddd whpshudwxuh?& , '' ' ' , '' ?$ ? $ ?$ 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 49 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller conditions: bod disabled; all oscillators and analog blocks disabled in the pdsleepcfg register (pdsleepcfg = 0x0000 18ff). fig 17. power-down mode: typical supply current i dd versus temperature for different supply voltages v dd wkt not running. fig 18. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd ddd whpshudwxuh?& , '' ' ' , '' ?$ ? $ ?$ 9 9 9 9 9 9 9 9 9 ddd whpshudwxuh?& , '' ' ' , '' ?$ ? $ ?$ 9 9 9 9 9 9 9 9 9 9 9 9
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 50 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller wkt running with internal 10 khz low-power oscillator. fig 19. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd (internal clock) wkt running with external 10 khz clock. clock inpu t waveform: square wave with rise time and fall time of 5 ns. fig 20. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd (external 10 khz input clock) ddd whpshudwxuh?& , '' ' ' , '' ?$ ? $ ?$ 9 9 9 9 9 9 9 9 9 9 9 9 ddd whpshudwxuh?& , '' ' ' , '' ?$ ? $ ?$ 9 9 9 9 9 9 9 9 9 9 9 9
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 51 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller wkt running with external 32 khz clock. clock inpu t waveform: square wave with rise time and fall time of 5 ns. fig 21. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd (external 32 khz input clock) ddd whpshudwxuh?& , '' ' ' , '' ?$ ? $ ?$ 9 9 9 9 9 9 9 9 9 9 9 9
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 52 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 11.4 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code accessing the periphe ral is executed. measured on a typical sample at t amb =25 ? c. the supply currents are shown for fro clock frequencies of 12 mhz and 30 mhz. table 14. power consumption for indi vidual analog and digital blocks peripheral typical supply current in a notes system clock frequency = n/a 12 mhz 30 mhz fro 89 - - system oscillator running; pll off; independent of main clock frequency; fro = 24 mhz. fro output disabled. system oscillator at 12 mhz 243 - - fro ru nning; pll off; independent of main clock frequency. watchdog oscillator 1 - - fro; pll off; independent of main clock frequency. bod 42 - - independent of main clock frequency. flash 273 - - - main pll 156 - - fro (24 mhz) running; main clock running at fro_div (12 mhz) clkout - 25 61 main clock divided by 4 in the clkoutdiv register. not connected to pin. rom - 35 86 - gpio + pin interrupt/pattern match - 159 384 gpio pins configured as outputs and set to low. direction and pin state are maintained if the gpio is disabl ed in the sysahbclkcfg register. swm - 85 206 - iocon - 80 193 - sctimer/pwm - 172 419 - ctimer 51 123 mrt - 102 245 - wwdt - 28 70 - i2c0 - 54 131 - i2c1 - 47 115 - i2c2 - 44 106 - i2c3 - 60 145 - spi0 - 43 106 - spi1 - 44 107 - usart0 - 53 128 - usart1 - 53 130 - usart2 - 46 90 -
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 53 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller usart3 - 58 142 - usart4 - 56 137 - comparator acmp - 79 144 - adc - 78 190 digital controller only. analog portion of the adc disabled in the pdruncfg register. - 78 190 combined analog and digital logic. adc enabled in the pdruncfg register and lpwrmode bit set to 1 in the adc ctrl register (adc in low-power mode). - 79 190 combined analog and digital logic. adc enabled in the pdruncfg register and lpwrmode bit set to 0 in the adc ctrl register (adc powered). dac 0 - 46 107 - dac 1 - 36 88 - capacitive touch - 49 117 - dma - 355 858 - crc - 36 83 - table 14. power consumption for indi vidual analog and digital blocks ?continued peripheral typical supply current in a notes system clock frequency = n/a 12 mhz 30 mhz
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 54 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 11.5 pin characteristics table 15. static characterist ics, pin characteristics t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit standard port pins config ured as digital pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled -0.510 [2] na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled -0.510 [2] na i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled -0.510 [2] na v i input voltage v dd ? 1.8 v; 5 v tolerant pins except pio0_6 0- 5v v dd = 0 v 0 - 3.6 v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage i oh = 4 ma; 2.5 v <= v dd <= 3.6 v v dd ? 0.4 - - v i oh = 3 ma; 1.8 v <= v dd < 2.5 v v dd ? 0.5 - - v v ol low-level output voltage i ol = 4 ma; 2.5 v <= v dd <= 3.6 v - - 0.5 v i ol = 3 ma; 1.8 v <= v dd < 2.5 v - - 0.5 v i oh high-level output current v oh =v dd ? 0.4 v; 2.5 v ? v dd ? 3.6 v 4- -ma v oh =v dd ? 0.5 v; 1.8 v ? v dd < 2.5 v 3- -ma i ol low-level output current v ol =0.5v 2.5 v ? v dd ? 3.6 v 4- -ma 1.8 v ? v dd < 2.5 v 3 - - ma i ohs high-level short-circuit output current v oh =0v [5] -- 45ma i ols low-level short-circuit output current v ol =v dd [5] -- 50ma i pd pull-down current v i =5v [6] 10 50 150 ? a i pu pull-up current v i =0v; 2.0 v ? v dd ? 3.6 v [6] 15 50 85 ? a 1.8 v ? v dd < 2.0 v 10 50 85 v dd lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 55 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled -0.510 [2] na v i input voltage v dd ? 1.8 v 0 - 5.0 v v dd = 0 v 0 - 3.6 v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage i oh = 20 ma; 2.5 v <= v dd < 3.6 v v dd ? 0.5 - - v i oh = 12 ma; 1.8 v <= v dd < 2.5 v v dd ? 0.5 - - v v ol low-level output voltage i ol =4 ma 2.5 v <= v dd < 3.6 v -- 0.5v i ol =3 ma 1.8 v <= v dd < 2.5 v -- 0.5v i oh high-level output current v oh =v dd ? 0.5 v; 2.5 v <= v dd < 3.6 v 20 - - ma v oh =v dd ? 0.5 v; 1.8 v <= v dd < 2.5 v 12 - - ma i ol low-level output current v ol =0.5v 2.5 v ? v dd ? 3.6 v 4- -ma 1.8 v ? v dd < 2.5 v 3 - - ma i ols low-level short-circuit output current v ol =v dd [5] -- 50ma i pd pull-down current v i =5v [6] 10 50 150 ? a i pu pull-up current v i =0v [6] ? 10 ? 50 ? 85 ? a v dd lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 56 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller [1] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. [2] based on characterization. not tested in production. [3] including voltage on outputs in 3-state mode. [4] 3-state outputs go into 3-state mode in deep power-down mode. [5] allowed as long as the current limit does not exceed the maximum current allowed by the device. [6] pull-up and pull-down currents are measured across t he weak internal pull-up/pull-down resistors. see figure 22 . [7] to v ss . i li input leakage current v i =v dd [7] -2 4 ? a v i = 5 v - 10 22 ? a table 15. static characterist ics, pin characteristics ?continued t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit fig 22. pin input/output current measurement aaa-010819 + - pin pio0_n i oh ipu - + pin pio0_n i ol i pd v dd a a
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 57 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 11.5.1 electrical pin characteristics conditions: v dd = 1.8 v; on pin pio0_12. conditions: v dd = 3.3 v; on pin pio0_12. fig 23. high-drive output: typical high-level output voltage v oh versus high-level output current i oh ddd , 2+ p$ 9 2+ 2 + 9 2+ 9 9 9 & & & & & & & & & & & & ddd , 2+ p$ 9 2+ 2 + 9 2+ 9 9 9 & & & & & & & & & & & & conditions: v dd = 1.8 v; on pins pio0_10 and pio0_11. conditions: v dd = 3.3 v; on pins pio0_10 and pio0_11. fig 24. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol ddd 9 2/ 9 , 2/ 2 / , 2/ p$ p $ p$ & & & & & & & & & & & & ddd 9 2/ 9 , 2/ 2 / , 2/ p$ p $ p$ & & & & & & & & & & & &
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 58 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller conditions: v dd = 1.8 v; standard port pins and high-drive pin pio0_12. conditions: v dd = 3.3 v; standard port pins and high-drive pin pio0_12. fig 25. typical low-level output current i ol versus low-level output voltage v ol ddd 9 2/ 9 , 2/ 2 / , 2/ p$ p $ p$ & & & & & & & & & & & & ddd 9 2/ 9 , 2/ 2 / , 2/ p$ p $ p$ & & & & & & & & & & & & conditions: v dd = 1.8 v; standard port pins. conditions: v dd = 3.3 v; standard port pins. fig 26. typical high-level output voltage v oh versus high-level output source current i oh ddd , 2+ p$ 9 2+ 2 + 9 2+ 9 9 9 & & & & & & & & & & & & ddd , 2+ p$ 9 2+ 2 + 9 2+ 9 9 9 & & & & & & & & & & & &
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 59 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller conditions: v dd = 1.8 v; standard port pins. conditions: v dd = 3.3 v; standard port pins. fig 27. typical pull-up current i pu versus input voltage v i ddd 9 , 9 , sx s x , sx ?$ ? $ ?$ & & & & & & & & & & & & ddd 9 , 9 , sx s x , sx ?$ ? $ ?$ & & & & & & & & & & & & conditions: v dd = 1.8 v; standard port pins. conditions: v dd = 3.3 v; standard port pins. fig 28. typical pull-down current i pd versus input voltage v i ddd 9 , 9 , sg s g , sg ?$ ? $ ?$ & & & & & & & & & & & & ddd 9 , 9 , sg s g , sg ?$ ? $ ?$ & & & & & & & & & & & &
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 60 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 12. dynamic characteristics 12.1 flash memory [1] number of program/erase cycles. [2] programming times are given for writing 64 bytes to the flash. t amb <= +85 ? c. flash programming with iap calls (see lpc84x user manual ). 12.2 fro [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 16. flash characteristics t amb = ? 40 ? c to +105 ? c. based on jedec nvm qualification. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 20 - years not powered 20 40 - years t er erase time page or multiple consecutive pages, sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms table 17. dynamic characteristic: fro t amb = ? 40 ? c to +105 ? c; 1.8 v ? v dd ? 3.6 v. symbol min typ [1] max unit fro clock frequency; condition: 0 ? c ? t amb ? 70 ? c f osc(rc) 18 -1 % 18 18 +1 % mhz f osc(rc) 24 -1 % 24 24 +1 % mhz f osc(rc) 30 -1 % 30 30 +1 % mhz fro clock frequency; condition: ? 20 ? c ? t amb ? 70 ? c f osc(rc) 18 -2 % 18 18 +1 % mhz f osc(rc) 24 -2 % 24 24 +1 % mhz f osc(rc) 30 -2 % 30 30 +1 % mhz fro clock frequency; condition: ? 40 ? c ? t amb ? 105 ? c f osc(rc) 18 -3.5 % 18 18 +2.5 % mhz f osc(rc) 24 -3.5 % 24 24 +2.5 % mhz f osc(rc) 30 -3.5 % 30 30 +2.5 % mhz
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 61 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller [1] typical ratings are not guaranteed. the va lues listed are at nom inal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ? 40 ? c to +105 ? c) is ? 40 %. [3] see the lpc84x user manual. 12.3 i/o pins [1] applies to standard port pins and reset pin. 12.4 wktclkin pin (w ake-up clock input) [1] assuming a square-wave input clock. 12.5 sctimer/pwm output timing table 18. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -9.4-khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 2300 - khz table 19. dynamic characteristics: i/o pins [1] t amb = ? 40 ? c to +105 ? c; 3.0 v ? v dd ? 3.6 v. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns table 20. dynamic characte ristics: wktclkin pin t amb = ? 40 ? c to +105 ? c; 1.8 v ? v dd ? 3.6 v. symbol parameter conditions min max unit f clk clock frequency deep power-down mode and power-down mode [1] -1 mhz deep-sleep, sleep, and active mode [1] -10mhz t chcx clock high time - 50 - ns t clcx clock low time - 50 - ns table 21. sctimer/pwm output dynamic characteristics t amb = ? 40 ? c to 105 ? c; 1.8 v <= v dd <= 3.6 v; c l = 10 pf. simulated skew (over process, voltage, and temperature) of any two sct output signals routed to standard i/o pins; sampled at the 50 % level of the falling or rising edge; values guaranteed by design. symbol parameter conditions min typ max unit t sk(o) output skew time - - - 6 ns
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 62 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 12.6 i 2 c-bus [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. table 22. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +105 ? c; values guaranteed by design. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus; on pins pio0_10 and pio0_11 01mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus; on pins pio0_10 and pio0_11 - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus; on pins pio0_10 and pio0_11 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus; on pins pio0_10 and pio0_11 0.26 - ? s t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus; on pins pio0_10 and pio0_11 0- ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus; on pins pio0_10 and pio0_11 50 - ns
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 63 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with res pect to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low per iod of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. also the acknowledge timing must meet this set-up time. fig 29. i 2 c-bus pins clock timing ddd w i 6'$ w i 6 w +''$7 6&/ i 6&/ w 9''$7 w +,*+ w /2: w 68'$7
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 64 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 12.7 spi interfaces the actual spi bit rate depends on the de lays introduced by the external trace, the external device, system clo ck (cclk), and capacitive loading. excluding delays introduced by external device and pcb, the maximum supported bit rate for spi master mode is 30 mbit/s, and the maximum supported bi t rate for spi slave mode is 1/(2 x 26 ns) = 19 mbit/s at 3.0v ? vdd ? 3.6v and 1/(2 x 42 ns) = 12 mbit/s at 1.8v ? vdd < 3.0v. remark: spi functions can be assigned to all digita l pins. the characteristics are valid for all digital pins except the open-drain pins pio0_10 and pio0_11. table 23. spi dynamic characteristics t amb = ? 40 ? c to 105 ? c; c l = 20 pf; input slew = 1 ns. simulated parameters sampled at the 30 % and 70 % level of the rising or falling edge; val ues guaranteed by design. de lays introduced by the external trace or external device are not considered. symbol parameter conditions min max unit spi master t ds data set-up time 1.8 v <= v dd <= 3.6 v 3 - ns t dh data hold time 1.8 v <= v dd <= 3.6 v 0 - ns t v(q) data output valid time 1.8 v <= v dd <= 3.6 v 0 5 ns spi slave t ds data set-up time 1.8 v <= v dd <= 3.6 v 4 - ns t dh data hold time 1.8 v <= v dd <= 3.6 v 1 - ns t v(q) data output valid time 3.0 v <= v dd <= 3.6 v 0 26 ns 1.8 v <= v dd < 3.0 v 0 42 ns
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 65 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller t cy(clk) = cclk/divval with cclk = system clock frequency. divval is the spi clock divider. see the lpc84x user manual . fig 30. spi master timing sck (cpol = 0) mosi (cpha = 1) ssel miso (cpha = 1) t cy(clk) t ds t dh t v(q) data valid (lsb) data valid t v(q) sck (cpol = 1) data valid (lsb) data valid mosi (cpha = 0) miso (cpha = 0) t ds t dh data valid (msb) data valid (msb) data valid data valid (lsb) data valid (lsb) t v(q) data valid (msb) data valid t v(q) aaa-014969 data valid (msb) data valid (msb) data valid (msb) data valid (msb) idle idle idle idle data valid (msb)
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 66 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 31. spi slave timing sck (cpol = 0) miso (cpha = 1) ssel mosi (cpha = 1) t cy(clk) t ds t dh t v(q) data valid (lsb) data valid t v(q) sck (cpol = 1) data valid (lsb) data valid miso (cpha = 0) mosi (cpha = 0) t ds t dh data valid (msb) data valid (msb) data valid data valid (lsb) data valid (lsb) t v(q) data valid (msb) data valid t v(q) aaa-014970 data valid (msb) data valid (msb) data valid (msb) data valid (msb) idle idle idle idle data valid (msb)
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 67 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 12.8 usart interface the actual usart bit rate depends on the de lays introduced by the external trace, the external device, system clo ck (cclk), and capacitive loading. excluding delays introduced by external device and pcb, the maximum supported bit rate for usart master synchronous mode is 10 mbit/s, and the maximum supported bit rate for usart slave synchronous mode is 10 mbit/s. remark: usart functions can be assigned to all di gital pins. the characteristics are valid for all digital pins except the ope n-drain pins pio0_10 and pio0_11. table 24. usart dynamic characteristics t amb = ? 40 ? c to 105 ? c; 1.8 v <= v dd <= 3.6 v unless noted otherwise; c l = 10 pf; input slew = 10 ns. simulated parameters sampled at the 30 %/70 % level of the falling or rising edge; values guaranteed by design. symbol parameter conditions min max unit usart master (in synchronous mode) t su(d) data input set-up time 3.0 v <= v dd <= 3.6 v 31 - ns 1.8 v <= v dd < 3.0 v 42 t h(d) data input hold time 0 - ns t v(q) data output valid time 0 7 ns usart slave (in synchronous mode) t su(d) data input set-up time 5 - ns t h(d) data input hold time 5 - ns t v(q) data output valid time 3.0 v <= v dd <= 3.6 v 0 35 ns 1.8 v <= v dd < 3.0 v 0 46 ns fig 32. usart timing un_sclk (clkpol = 0) txd rxd t cy(clk) t su(d) t h(d) t v(q) start bit0 t vq) un_sclk (clkpol = 1) start bit0 bit1 bit1 aaa-015074
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 68 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 12.9 wake-up process [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the wake-up time measured is the time between when a gpio input pin is trigger ed to wake the device up from the low power modes and from when a gpio output pin is set in the interrupt service routine (isr) wake-up handler. isr is located in sram. [3] fro enabled, all peripherals off. pll disabled. [4] wkt disabled. wake up from deep power-down causes the part to go through entire reset process. the wake-up time measured is the time between when the reset pin is triggered to wake the device up and when a gpio output pin is set in the reset handler. table 25. dynamic characteristic: typica l wake-up times from low power modes v dd = 3.3 v;t amb =25 ? c; using fro (12mhz) as the system clock. symbol parameter conditions min typ [1] max unit t wake wake-up time from sleep mode [2] [3] -2.4 - ? s from deep-sleep mode [2] -2.5 - ? s from power-down mode [2] -50 - ? s from deep power-down mode; wkt disabled; using reset pin. [4] -250 - ? s
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 69 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 13. characteristics of analog peripherals 13.1 bod [1] interrupt levels are selected by writing the le vel value to the bod control register bodctrl, see the lpc84x user manual . interrupt level 0 is reserved. table 26. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 1 assertion - 2.25 - v de-assertion - 2.38 - v interrupt level 2 assertion - 2.55 - v de-assertion - 2.66 - v interrupt level 3 assertion - 2.84 - v de-assertion - 2.92 - v reset level 0 assertion - 1.84 - v de-assertion - 1.97 - v reset level 1 assertion - 2.05 - v de-assertion - 2.18 - v reset level 2 assertion - 2.35 - v de-assertion - 2.47 - v reset level 3 assertion - 2.63 - v de-assertion - 2.76 - v
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 70 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 13.2 adc [1] the input resistance of adc channel 0 is higher than for all other channels. see figure 33 . [2] in the adc trm register, set vrange = 0 (default). [3] in the adc trm register, set vrange = 1. [4] based on characterization. not tested in production. [5] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 34 . [6] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 34 . [7] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 34 . [8] the full-scale error voltage or gain error (e g ) is the difference between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 34 . [9] t amb = 25 ? c; maximum sampling frequency f s = 1.2 msamples/s and analog input capacitance c ia = 26 pf. [10] input impedance z i (see section 13.2.1 ? adc input impedance ? ) is inversely proportional to the sampling frequency and the total input capacity including c ia and c io : z i ? 1 / (f s ? c i ). see table 13 for c io . table 27. 12-bit adc static characteristics t amb = ? 40 ? c to +105 ? c unless noted otherwise; v dd = v dda = 2.4 v to 3.6 v; vrefp = v dd = v dda ; vrefn = v ss . symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v v ref reference voltage on pin vrefp 2.4 - v dda v c ia analog input capacitance - - 26 pf f clk(adc) adc clock frequency [2] -- 30mhz f s sampling frequency [2] - - 1.2 msamples/s e d differential linearity error [5][4] - ? 3.0 - lsb e l(adj) integral non-linearity [6][4] - ? 2.0 - lsb e o offset error [7][4] - ? 3.5 - lsb v err(fs) full-scale error voltage [8][4] -0.1 -% z i input impedance f s = 1.2 msamples/s [1][9][10] 0.1 - - m ?
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 71 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 33. 12-bit adc characteristics aaa-016908 4095 4094 4093 4092 4091 (2) (1) 4096 4090 4091 4092 4093 4094 4095 7 123456 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 lsb (ideal) code out vrefp - vrefn 4096 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 72 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 13.2.1 adc input impedance figure 34 shows the adc input impedance. in this figure: ? adcx represents adc input channel 0. ? adcy represents adc input channels 1 to 11. ? r 1 and r sw are the switch-on resistance on the adc input channel. ? if adc input channel 0 is selected, th e adc input signal goes through r 1 + r sw to the sampling capacitor (c ia ). ? if adc input channels 1 to 11 are selected, the adc input signal goes through r sw to the sampling capacitor (c ia ). ? typical values, r 1 = 2.5 k ? , r sw = 25 ? ? see ta b l e 11 for c io . ? see ta b l e 2 7 for c ia . fig 34. adc input impedance dac adc r sw r 1 c ia adcx adcy c io c io aaa-017600
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 73 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 13.3 comparator and internal voltage reference table 28. internal voltage reference static and dynamic characteristics t amb = ? 40 ? c to +105 ? c; v dd = 3.3 v; hysteresis disabled in the comparator ctrl register. symbol parameter conditions min typ max unit v o output voltage t amb = 25 ? c to 105 ? c 860 - 940 mv t amb = 25 ? c 904 mv v dd = 3.3 v; characterized through bench measurements on typical samples. fig 35. typical internal voltage reference output voltage aaa-014424 -40 -10 20 50 80 110 0.890 0.895 0.900 0.905 0.910 temperature (c) v ref r e f v o (mv) ( m v ) (v) table 29. comparator characteristics t amb = ? 40 ? c to +105 ? c unless noted otherwise; v dd = 1.8 v to 3.6 v. symbol parameter conditions min typ max unit static characteristics v ref(cmp) comparator reference voltage pin acmpv ref 1.5 - 3.6 v i dd supply current vp > vm; t amb = 25 c; v dd = 3.3 v [2] -90 - ? a vm > vp; t amb = 25 c; v dd = 3.3 v [2] -60 - ? a v ic common-mode input voltage 0 - v dd v dv o output voltage variation 0 - v dd v v offset offset voltage v ic = 0.1 v; v dd = 3.0 v [2] -3 - mv v ic = 1.5 v; v dd = 3.0 v [2] -3 - mv v ic = 2.9 v; v dd = 3.0v [2] -6 - mv dynamic characteristics t startup start-up time nominal process; v dd = 3.3 v; t amb = 25 c -13 - ? s
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 74 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller [1] c l = 10 pf [2] characterized on typical samp les, not tested in production. [3] input hysteresis is relative to the referenc e input channel and is software programmable. [4] 100 mv overdrive corresponds to a square wave from 50 mv below the reference (v ic ) to 50 mv above the reference. [1] characterized on typical samples, not tested in production. t pd propagation delay high to low; v dd = 3.0 v; t amb = 105 c v ic = 0.1 v; 100 mv overdrive input [1][2][4] - 150 -ns v ic = 0.1 v; rail-to-rail input [1][2] -250- ns v ic = 1.5 v; 100 mv overdrive input [1][2][4] -150- ns v ic = 1.5 v; rail-to-rail input [1][2] -170- ns v ic = 2.9 v; 100 mv overdrive input [1][2][4] -180- ns v ic = 2.9 v; rail-to-rail input [1][2] -70 - ns t pd propagation delay low to high; v dd = 3.0 v; t amb = 105 c v ic = 0.1 v; 100 mv overdrive input [1][2][4] - 260 -ns v ic = 0.1 v; rail-to-rail input [1][2] -90 - ns v ic = 1.5 v; 100 mv overdrive input [1][2][4] -270- ns v ic = 1.5 v; rail-to-rail input [1][2] -220- ns v ic = 2.9 v; 100 mv overdrive input [1][2][4] -190- ns v ic = 2.9 v; rail-to-rail input [1][2] -700- ns v hys hysteresis voltage positive hysteresis; v dd = 3.0 v; v ic = 1.5 v; t amb = 105 c; settings: 5 mv [3] -6 - mv 10 mv - 12 - mv 20 mv - 22 - mv v hys hysteresis voltage negative hysteresis; v dd = 3.0 v; v ic = 1.5 v; t amb = 105 c; settings: 5 mv [1][3] - 7 -mv 10 mv - 13 - mv 20 mv - 23 - mv r lad ladder resistance - - 1 - m ? table 29. comparator characteristics ?continued t amb = ? 40 ? c to +105 ? c unless noted otherwise; v dd = 1.8 v to 3.6 v. symbol parameter conditions min typ max unit table 30. comparator voltage ladder dynamic characteristics t amb = ? 40 ? c to +105 ? c; v dd = 1.8 v to 3.6 v. symbol parameter conditions min typ max unit t s(pu) power-up settling time to 99% of voltage ladder output value [1] -17- ? s t s(sw) switching settling time to 99% of voltage ladder output value [1] -18- ? s
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 75 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller [1] characterized though limited samples. not tested in production. [2] all peripherals except comparator, temperature sensor, and fro turned off. 13.4 dac [1] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c) and v dd = v dda = 3.6 v. [2] characterized through bench measurements, not tested in production. [3] dac output voltage depends on the voltage divider ratio of the r out and external load resistance. table 31. comparator voltage ladder reference static characteristics v dd = 1.8 v to 3.6 v. t amb = -40 ? c to + 105 ? c; external or internal reference. symbol parameter conditions min typ [1] max unit e v(o) output voltage error decimal code = 00 [2] - ? 6- mv decimal code = 08 - ? 1- % decimal code = 16 - ? 1- % decimal code = 24 - ? 1- % decimal code = 30 - ? 1- % decimal code = 31 - ? 1- % table 32. 10-bit dac electr ical characteristics v dd = v dda = 2.7 v to 3.6 v; t amb = ? 40 ? c to +105 ? c unless otherwise specified symbol parameter min typ max unit e d differential linearity error [1][2] -0.4- lsb e l(adj) integral non-linearity [1][2] -6.0- lsb e o offset error [1][2] - ? 57.0 - mv e g gain error [1][2] - ? 36.0 - mv c l load capacitance - 200 - pf r out pio0_17/dacout_0 pin resistance [3] - 90 200 ? r out pio0_29/dacout_1 pin resistance [3] -2 5 k ? v out output voltage range 0.175 - v dda -0.175 v
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 76 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 14. application information 14.1 start-up behavior figure 36 shows the start-up timing after reset. the fro 12 mhz oscillator provides the default clock at reset and provides a clean system clock shortly af ter the supply pins reach operating voltage. fig 36. start-up timing table 33. typical start-up timing parameters parameter description value t a fro start time ? 26 ? s t b internal reset de-asserted 101 ? s t c boot time 51 ? s aaa-027486 valid threshold = 1.8 v processor status v dd fro status internal reset gnd boot time user code boot code execution finishes; user code starts fro starts supply ramp-up time t b s t a s t c s
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 77 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 14.2 xtal oscillator in the xtal oscillator circ uit, only the crystal (xtal) and the capacitances c x1 and c x2 need to be connected externally on xtalin and xtalout. see figure 37 . for best results, it is very critical to sele ct a matching crystal fo r the on-chip oscillator. load capacitance (cl), series resistance (rs), and drive level (dl) are important parameters to consider while choosing the cr ystal. after selecting the proper crystal, the external load capacitor c x1 and c x2 values can also be gen erally determined by the following expression: c x1 = c x2 = 2c l ? (c pad + c parasitic ) where: c l - crystal load capacitance c pad - pad capacitance of the xtalin and xtalout pins (~3 pf). c parasitic ? parasitic or stray capacitance of external circuit. although c parasitic can be ignored in general, the actual board layout and placement of external components influences the optimal values of external load capacitors. therefore, it is recommended to fine tune the values of external load capacitors on actual hardware board to get the accurate clock frequency. for fine tuning, measure the clock on the xtalout pin and optimize the values of external load capacitors for minimum frequency deviation. fig 37. xtal oscillator components aaa-025725 lpcxxxx xtalin xtalout c x2 c x1 xtal = c l c p r s l
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 78 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 14.2.1 xtal printed circuit board (pcb) design guidelines ? connect the crystal and external load capacitors on the pcb as close as possible to the oscillator input and output pins of the chip. ? the length of traces in the o scillation circuit should be as short as possible and must not cross other signal lines. ? ensure that the load capacitors cx1, cx2, and cx3, in case of third overtone crystal usage, have a common ground plane. ? loops must be made as small as possible to minimize the noise coupled in through the pcb and to keep the parasitics as small as possible. ? lay out the ground (gnd) pattern under crystal unit. ? do not lay out other signal lines under crystal unit for multi-layered pcb. 14.2.2 xtal input the input voltage to the on-chip oscillators is limited to 1.95 v. if the oscillator is driven by a clock in slave mode, it is recommended to couple the input through a capacitor with c i = 100 pf. to limit the input voltage to the specif ied range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. in slave mode the input clock signal should be coupled with a capacitor of 100 pf ( figure 38 ), with an amplitude between 200 mv (rms) and 1000 mv (rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. 14.3 connecting power, clo cks, and debug functions figure 39 shows the basic board connections used to power the lpc84x, connect the external crystal, and pr ovide debug capabilities vi a the serial wire port. fig 38. slave mode operation of the on-chip oscillator /3& ;7$/,1 & l s) & j ddd
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 79 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller (1) see section 14.2 ? xtal oscillator ? for the values of c1 and c2. (2) position the decoupling capacitors of 0.1 f and 0.01 f as close as possible to the v dd pin. add one set of decoupling capacitors to each v dd pin. (3) position the decoupling capacitors of 0.1 f as close as possible to the vrefn and v dd pins. the 10 f bypass capacitor filters the power line. tie vrefp to v dd if the adc is not used. tie vrefn to v ss if adc is not used. (4) uses the arm 10-pin interface for swd. (5) when measuring signals of low frequency, use a low-pass filter to remove noise and to improve adc performance. also see ref. 4 . (6) external pull-up resistors on swdio and swclk pins are opt ional because these pins hav e an internal pull-up enabled by default. fig 39. power, clock, and debug connections pio0_12 adc_0 pio0_8/xtalin pio0_9/xtalout v dd vrefp pio0_6/adc_1/acmpv ref vrefn lpc84x 3.3 v dgnd note 5 note 5 (adc_1), note 3 (acmpv ref ) c1 c2 note 1 dgnd dgnd note 2 note 3 0.01 f 0.1 f 3.3 v agnd agnd agnd 10 f 0.1 f 0.1 f isp select pin aaa-026592 swdio/pio0_2 swclk/pio0_3 resetn/pio0_5 v ss 3.3 v dgnd dgnd 1 3 5 7 9 2 4 6 8 10 n.c. n.c. n.c. swd connector (6) (4) (6) 3.3 v ~10 k - 100 k ~10 k - 100 k 3.3 v
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 80 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 14.4 i/o power consumption i/o pins are contributing to the overall dynamic and static power consumption of the part. if pins are configured as digital inputs, a st atic current can flow depending on the voltage level at the pin and the setting of the internal pull-up and pull-down resistors. this current can be calculated using the parameters r pu and r pd given in ta b l e 1 5 for a given input voltage v i . for pins set to output, the current drive strength is given by parameters i oh and i ol in ta b l e 1 5 , but for calculating the total static current, you also need to consider any external loads connected to the pin. i/o pins also contribute to the dynamic power consumption when the pins are switching because the v dd supply provides the current to charge and discharge all internal and external capacitive loads con nected to the pin in addition to powering the i/o circuitry. the contribution from the i/o switching current i sw can be calculated as follows for any given switching frequency f sw if the external capacitive load (c ext ) is known (see ta b l e 1 5 for the internal i/o capacitance): i sw = v dd x f sw x (c io + c ext ) 14.5 termination of unused pins ta b l e 3 4 shows how to terminate pins that are not used in the application. in many cases, unused pins may should be connected externally or configured correctly by software to minimize the overall power consumption of the part. unused pins with gpio function should be configured as outputs set to low with their internal pull-up disabled. to configure a gpio pin as output and drive it low, select the gpio function in the iocon register, select ou tput in the gpio dir register, and write a 0 to the gpio port register for that pin. di sable the pull-up in the pin?s iocon register. in addition, it is recommended to configure all gpio pins that are not bonded out on smaller packages as outputs driven low with their internal pull-up disabled. [1] i = input, o = output, ia = inactive (no pull- up/pull-down enabled), f = floating, pu = pull-up. table 34. termination of unused pins pin default state [1] recommended termination of unused pins reset /pio0_5 i; pu in an applicati on that does not use the reset pin or its gpio function, the termination of this pin depends on w hether deep power-down mode is used: ? deep power-down used: connect an external pull-up resistor and keep pin in default state (input, pull-up enabled) during all other power modes. ? deep power-down not used and no external pull-up connected: can be left unconnected if internal pull-up is disabled and pin is driven low and configured as output by software. all pion_m (not open-drain) i; pu can be left unconnected if driven low and configured as gp io output with pull-up disabled by software. pion_m (i2c open-drain) ia can be left unconnected if driven low and configured as gpio output by software. vrefp - tie to vdd. vrefn - tie to vss.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 81 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 14.6 pin states in di fferent power modes [1] default and programmed pin states are retained in sleep, deep-sleep, and power-down modes. table 35. pin states in different power modes pin active sleep deep-sleep/power- down deep power-down pion_m pins (not i2c) as configured in the iocon [1] . default: internal pull-up enabled. floating. open-drain i2c-bus pins as configured in the iocon [1] . floating. reset reset function enabled. default: input, internal pull-up enabled. reset function disabled; floating; if the part is in deep power-down mode, the reset pin needs an external pull-up to reduce power consumption. wakeup as configured in the iocon [1] . wakeup function inactive. wake-up function enabled; can be disabled by software.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 82 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 15. package outline fig 40. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 83 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 41. package outline sot314-2 (lqfp64) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 84 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 42. package outline hvqfn33 (5 x 5 x 0.85 mm) references outline version european projection issue date iec jedec jeita mo-220 hvqfn33f_po 11-10-11 11-10-17 unit (1) mm max nom min 0.85 0.05 0.00 0.2 5.1 4.9 3.75 3.45 5.1 4.9 3.75 3.45 0.5 3.5 a 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm bc 0.30 0.18 d (1) a (1) d h e (1) e h ee 1 e 2 l 3.5 vw 0.1 0.1 y 0.05 0.5 0.3 y 1 0.05 0 2.5 5 mm scale 1/2 e a c b v c w terminal 1 index area a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area 1/2 e
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 85 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 43. package outline hvqfn48 7 x 7x 0.85 mm (sot619-1) references outline version european projection issue date iec jedec jeita sot619-1 mo-220 sot619-1_po 02-10-18 12-11-22 unit (1) mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 7.1 7.0 6.9 5.25 5.10 4.95 5.25 5.10 4.95 7.1 7.0 6.9 0.5 0.4 0.3 0.5 5.5 0.1 a dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included hvqfn48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm sot619-1 a 1 b 0.30 0.21 0.18 cdd h ee h ee 1 e 2 5.5 lv 0.1 w 0.05 y 0.05 y 1 0 2.5 5 mm scale a a 1 c detail x l e h d h b 13 24 48 37 36 25 12 1 d e terminal 1 index area terminal 1 index area 1/2 e a c b v wc b c a y e 1 e 2 1/2 e c y 1 e x e
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 86 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 16. soldering fig 44. reflow soldering for the lqfp48 package sot313-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp48 package ax bx gx gy hy hx ay by p1 d2 (8 ) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 10.350 p2 0.560 10.350 7.350 7.350 p1 0.500 0.280 c 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout p2
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 87 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 45. reflow soldering for the lqfp64 package sot314-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp64 package ax bx gx gy hy hx ay by p1 p2 d2 (8 ) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 13.300 13.300 10.300 10.300 p1 0.500 p2 0.560 0.280 c 1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 88 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 46. reflow soldering of the hvqfn48 package (7x7) 1 of 3
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 89 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 47. reflow soldering of the hvqfn48 package (7x7) 2 of 3
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 90 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 48. reflow soldering of the hvqfn48 package (7x7) 3 of 3
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 91 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller fig 49. reflow soldering of the hvqfn48 package (7x7) sot619-1 footprint information for reflow soldering of hvqfn48 package dimensions in mm ax ay bx by d slx sly spx tot spy tot spx spy gx gy hx hy 8.000 8.000 6.200 6.200 p 0.500 0.290 c 0.900 5.100 5.100 3.000 3.000 0.750 0.750 7.300 7.300 8.250 8.250 nspx nspy 33 sot619-1_fr occupied area ax bx slx gx gy hy hx ay by sly p 0.025 0.025 d (0.105) spx tot spy t o t nspx nspy spx spy solder land plus solder paste solder land solder paste deposit c generic footprint pattern refer to the package outline drawing for actual layout issue date 07-05-07 09-06-15
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 92 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 17. abbreviations 18. references [1] lpc84x user manual um11029: [2] lpc84x errata sheet: [3] i2c-bus specification um10204 . [4] technical note adc design guidelines: http://www.nxp.com/documents /technical_note/tn00009.pdf table 36. abbreviations acronym description ahb advanced high-performance bus apb advanced peripheral bus bod brownout detection gpio general-purpose input/output pll phase-locked loop rc resistor-capacitor spi serial peripheral interface smbus system management bus tem transverse electromagnetic uart universal asynchronous receiver/transmitter
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 93 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 19. revision history table 37. revision history document id release date data sheet status change notice supersedes lpc84x v.1.7 20180227 product data sheet - lpc84x v.1.6 modifications: ? updated table 17 ? dynamic characteristic: fro ? : max values: fro clock frequency; condition: ? 20 ? c ? t amb ? 70 ? c and fro clock frequency; condition: ? 40 ? c ? t amb ? 105 ? c. lpc84x v.1.6 20180216 product data sheet - lpc84x v.1.5 modifications: ? updated reflow soldering of the hvqfn48 pack age to add three figures: figure 46 ?reflow soldering of the hvqfn48 package (7x7) 1 of 3? , figure 47 ?reflow soldering of the hvqfn48 package (7x7) 2 of 3? and figure 48 ?reflow sol dering of the hvqfn48 package (7x7) 3 of 3?. lpc84x v.1.5 20171214 product data sheet - lpc84x v.1.4 modifications: ? updated table 25 ?dynamic characteristic: typical wake-up times from low power modes?. ? removed remark from section 8.17 ?capacitive touch interface?: remark: evaluation kits and software packages for capacitive touch will be available in late q3-2017. lpc84x v.1.4 20171128 product data sheet - lpc84x v.1.3 modifications: ? updated table 17 ?dynamic characteristic: fro?. added conditions ??? 20 ? c ? t amb ? 70 ? c and ? 40 ? c ? t amb ? 105 ? c. ? updated figure 8 ?lpc84x ahb memory mapping?. ? updated table notes: table 15 ?static c haracteristics, pin characteristics?. ? updated table 14 ?power consumption for individual analog and digital blocks?: fro typical supply current in a is 89. lpc84x v.1.3 20170809 product data sheet - lpc84x v.1.2 modifications: ? updated table 9 ?limiting values?: added max va lues for supply and gr ound pins for lqfp48, hvqfn48, and hvqfn33 packages. ? updated table 1 ?ordering information?: descr iption of part number lpc844m201jhi48 and package name, hvqfn48. lpc84x v.1.2 20170801 product data sheet - lpc84x v.1.1 modifications: ? updated table 7 ?peripheral configuration in reduced power modes? and table 8 ?wake-up sources for reduced power modes?: cap touch interrupt can wake up from power down mode. ? updated table 2 ?ordering options?. lpc845m 301jhi33 does not have capacitive touch. lpc84x v.1.1 20170623 product data sheet - lpc84x v.1 modifications: ? updated table 27 ?12-bit adc static characteristics?. ? added a remark to section 8.17 ?capacitive to uch interface?: evaluation kits and software packages for capacitive touch will be available in late q3-2017. lpc84x v.1 20170619 product data sheet - -
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 94 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 95 of 97 nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 20.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc84x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights rese rved. product data sheet rev. 1.7 ? 27 february 2018 96 of 97 continued >> nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 7 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 8 functional description . . . . . . . . . . . . . . . . . . 17 8.1 arm cortex-m0+ core . . . . . . . . . . . . . . . . . . . 17 8.2 on-chip flash program memo ry . . . . . . . . . . . 17 8.3 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 17 8.4 faim memory . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.5 on-chip rom . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.6 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.7 nested vectored interrupt controller (nvic) . 19 8.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.7.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 19 8.8 system tick timer . . . . . . . . . . . . . . . . . . . . . . 19 8.9 i/o configuration . . . . . . . . . . . . . . . . . . . . . . . 19 8.9.1 standard i/o pad configuration . . . . . . . . . . . . 20 8.10 switch matrix (swm) . . . . . . . . . . . . . . . . . . . 21 8.11 fast general-purpose parallel i/o (gpio) . . . 21 8.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.12 pin interrupt/pattern match engine . . . . . . . . . 21 8.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.13 dma controller . . . . . . . . . . . . . . . . . . . . . . . . 22 8.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.13.2 dma trigger input mux (trigmux). . . . . . . . 23 8.14 usart0/1/2/3/4 . . . . . . . . . . . . . . . . . . . . . . . 23 8.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.15 spi0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.16 i 2 c-bus interface (i 2 c0/1/2/3) . . . . . . . . . . . . . 24 8.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.17 capacitive touch interface . . . . . . . . . . . . . . . 24 8.18 sctimer/pwm . . . . . . . . . . . . . . . . . . . . . . . . 25 8.18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.18.2 sctimer/pwm input mux (input mux). . . . 26 8.19 ctimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.19.1 general-purpose 32- bit timers/external event counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.19.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.20 multi-rate timer (mrt) . . . . . . . . . . . . . . . . . 27 8.20.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.21 windowed watchdog ti mer (wwdt) . . . . . . 27 8.21.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.22 self-wake-up timer (wkt) . . . . . . . . . . . . . . 28 8.22.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.23 analog comparator (acmp) . . . . . . . . . . . . . . 28 8.23.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.24 analog-to-digital converter (adc). . . . . . . . . 29 8.24.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.25 digital-to-analog converter (dac). . . . . . . . . 30 8.25.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.26 crc engine . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.26.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.27 clocking and power control . . . . . . . . . . . . . . 31 8.27.1 crystal and internal osci llators . . . . . . . . . . . . 31 8.27.1.1 free running oscillator (fro) . . . . . . . . . . . 31 8.27.1.2 crystal oscillator (sysosc) . . . . . . . . . . . . . . 31 8.27.1.3 internal low-power oscillator and watchdog oscillator (wdosc) . . . . . . . . . . . . . . . . . . . . 31 8.27.2 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.27.3 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.27.4 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.27.5 power control . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.27.5.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.27.5.2 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 36 8.27.5.3 power-down mode . . . . . . . . . . . . . . . . . . . . . 36 8.27.5.4 deep power-down mode . . . . . . . . . . . . . . . . 36 8.27.6 wake-up process . . . . . . . . . . . . . . . . . . . . . . 38 8.28 system control . . . . . . . . . . . . . . . . . . . . . . . . 39 8.28.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.28.2 brownout detection . . . . . . . . . . . . . . . . . . . . 39 8.28.3 code security (code read protection - crp) 40 8.28.4 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.28.5 ahblite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.29 emulation and debugging . . . . . . . . . . . . . . . 41 9 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 42 10 thermal characteristics . . . . . . . . . . . . . . . . . 44 11 static characteristics . . . . . . . . . . . . . . . . . . . 45 11.1 general operating conditions . . . . . . . . . . . . . 45 11.2 power-up ramp conditions . . . . . . . . . . . . . . . 46 11.3 power consumption . . . . . . . . . . . . . . . . . . . . 47 11.4 peripheral power consumption . . . . . . . . . . . 52 11.5 pin characteristics . . . . . . . . . . . . . . . . . . . . . 54 11.5.1 electrical pin characteristics. . . . . . . . . . . . . . 57 12 dynamic characteristics. . . . . . . . . . . . . . . . . 60 12.1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . 60 12.2 fro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
nxp semiconductors lpc84x 32-bit arm cortex-m0+ microcontroller ? nxp semiconductors n.v. 2018. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 27 february 2018 document identifier: lpc84x please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 12.3 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.4 wktclkin pin (wake-up cl ock input) . . . . . . 61 12.5 sctimer/pwm output timing . . . . . . . . . . . . . 61 12.6 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.7 spi interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.8 usart interface. . . . . . . . . . . . . . . . . . . . . . . 67 12.9 wake-up process . . . . . . . . . . . . . . . . . . . . . . 68 13 characteristics of analog peripherals . . . . . . 69 13.1 bod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13.2 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 13.2.1 adc input impedance. . . . . . . . . . . . . . . . . . . 72 13.3 comparator and internal voltage reference . . 73 13.4 dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 14 application information. . . . . . . . . . . . . . . . . . 76 14.1 start-up behavior . . . . . . . . . . . . . . . . . . . . . . 76 14.2 xtal oscillator . . . . . . . . . . . . . . . . . . . . . . . . 77 14.2.1 xtal printed circuit board (pcb) design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.2.2 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.3 connecting power, clocks, and debug functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.4 i/o power consumption. . . . . . . . . . . . . . . . . . 80 14.5 termination of unused pins. . . . . . . . . . . . . . . 80 14.6 pin states in different power modes . . . . . . . . 81 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 82 16 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 92 18 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 19 revision history . . . . . . . . . . . . . . . . . . . . . . . . 93 20 legal information. . . . . . . . . . . . . . . . . . . . . . . 94 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 94 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 20.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 95 21 contact information. . . . . . . . . . . . . . . . . . . . . 95 22 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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